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stopwatch
- 基于Xilinx Spartan3E的秒表，能实现计时两次的功能-Based on the Xilinx Spartan3E stopwatch, time to achieve the functions of the two
61EDA_D408
- 跑表计时器 用xilinx里的各种软件都实现了一遍-Stopwatch timer with Xilinx
stopwatch
- The program is written in verilog to accomplish functions of a stopwatch. It can be implemented in Xilinx FPGA spartan 3 board.
stopwatchVHDL
- Stopwatch program in VHDL using Xilinx.
ModelsimVerilogWatch
- Stopwatch Design - ModelSim Vlog Tutorial Required Software: - Model Technology Modelsim 5.4a - Xilinx Development System 3.1i CONTROLS Inputs: * CLK -System clock for the Watch design. * STRTSTOP -Starts and stops the stoopwatch
seccount
- 用VHDL语言设计电子数字秒表。包含相关文件及说明，用户可以在Xilinx ISE 环境下运行。-With VHDL language design digital stopwatch. Contains the corresponding code and all documents. Users can Xilinx ISE environment in operation
DigiClock_v1.0
- 多功能数字钟：包含默认模式、设置模式、闹钟模式和跑表模式。已在ISE10.1工具烧录成功，烧录开发板Xilinx Spartan 3 xc3s400 pq205 speed -4 开发板烧录成功-Multi-function digital clock: contains the default mode, setting mode, alarm mode and stopwatch mode. The source code has been successfully burned in IS
runningclock
- verilog HDL实现跑表设计，开发环境为xilinx，fpga芯片为spartan系列。-verilog HDL the Stopwatch design and development environment for the spartan xilinx, fpga chip series.
MyDigiditClock2
- 一个简单的基于赛灵思公司的nexys3的秒表计时器。能够实现计时的开始、暂停、复位、切换显示百分秒。无需连接任何其他的硬件。-Based on a simple Xilinx nexys3 stopwatch timer. Start timing can be achieved, pause, reset, switch the display percentile seconds. Without connecting any additional hardware.
Timer
- 基于verilog xilinx spartan 3e100的秒表计时器-Based verilog xilinx spartan 3e100 stopwatch timer
stopwatch
- 毫秒级跑表设计,基于xilinx公司的Spartan3,用microblaze嵌入式方式实现的。-millisecond stopwatch design
FPGA
- 韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验-Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and key
szmb
- 用VHDL语言基于ISE，在XILINX FPGA开发板上编写的数字秒表程序(Using VHDL language, based on ISE, in the XILINX FPGA development board prepared by the digital stopwatch program)