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LM3S_UART_FIFO_IntTx
- UART(通用异步收发器)\LM3S系列UART例程:FIFO中断方式发送数据-UART (Universal Asynchronous Receiver Transmitter) \ LM3S series UART routines: FIFO interrupt mode to send data
fifo16
- 异步的FIFO。带TESTbenchi。希望对大家有帮助啊-Asynchronous FIFO. With TESTbenchi. I hope to have everyone help ah
fifo16_16
- 异步的fifo,写时钟和读时钟相互独立,能够对数据进行缓存处理。希望对大家有用-Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful
APC
- APC中文叫异步过程调用(APC)是NT异步处理体系结构中的一个基础部分。Alertable IO(告警IO)提供了更有效的异步通知形式,当IO请求完成后,一旦线程进入可告警状态,回调函数将会执行,也就是一个APC的过程。线程进入告警状态时,内核将会检查线程的APC队列,如果队列中有APC,将会按FIFO方式依次执行。如果队列为空,线程将会挂起等待事件对象。以后的某个时刻,一旦APC进入队列,线程将会被唤醒执行APC。-APC called asynchronous procedure call
DWC_mctl_ddr_fifo
- ASIC设计中各种同步异步的FIFO实现的verilog source code, 参数可配置 -almost all kinds of FIFO with verilog source code, parametes configuration
fifoas
- 异步时序的FIFO,实现了异步逻辑的电路,可综合,通过了验证-Asynchronous timing FIFO, implement asynchronous logic circuits can be integrated through the verification
AsynCFIFO
- 跨时钟域,异步的FIFO,利用指针移动,数据不移动,通过两级锁存消除跨时钟域的信号竞争-Cross clock domains and asynchronous FIFO, use the pointer to move, do not move the data, eliminating cross clock domain signal through a two-stage competition latch
a_vhd_16550_uart_latest.tar
- 这个芯的设计是与国家半导体PC16550D兼容 UART(通用异步接收器/发送器)。一些差异:该FIFO的始终启用 不支持置顶奇偶-This core is designed to be a compatible with the National Semiconductor PC16550D UART (Universal Asynchronous Receiver/Transmitter).Some differences: The FIFO’s are always enabl
FX2LP-firmware
- cy7c68013 同步Slave fifo传输 固件。 经测试,速度可以达到每秒40MB以上。 网上很多代码均为异步,速度最多只能到10多MB。注意:因为和FPGA配套,时钟是外部提供,若有不明,可以联系我。-cy7c68013 slave fifo sync transfer firmware. Speed up to 40MB/s.