查看会员资料
用 户 名:李***
发送消息- Email:用户隐藏
- Icq/MSN:
- 电话号码:
- Homepage:
- 会员简介:
最新会员发布资源
VerilogDesignand-test_PdfPCode
- Verilog 设计与验证源码+PDF,经典教程,对与RTL和状态机的理解有很大帮助,适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.