搜索资源列表
Oscillator_Internal_PLL
- Silicon LABs C8051F121 倍频程序 将内部25MHz晶振倍频为100MHz-The 8051F121 multiplier program
N_bit_even_divide
- 介绍了常用的偶数倍频器的使用，以及源代码-Even doubler use, as well as the source code
VGA
- 这是我自己做的一个FPGA控制VGA，800*600*60，用的是20Mhz倍频到40MHz做的-This is a FPGA project using for VGA control
Pll_prj
- FPGA中PLL模块的测试代码，代码通过例化一个PLL将25MHz系统时钟倍频到50MHz，然后通过两个不同频率时钟控制两个LED灯闪烁，通过闪烁频率可用观察PLL倍频效果-The FPGA PLL module test code, the code by instantiating a PLL to 25MHz system clock frequency doubling to 50MHz, and then by two different frequency clock control
ADS1248_C8051F350
- ads1248 在C8051F350 上的应用，C8051F350采用内部时钟，PLL倍频，串口115200BPS返回数据，ADS1248放大16倍，40SPS。-The ads1248 In the application on the C8051F350, C8051F350 internal clock PLL multiplier, the serial 115200BPS return data, ADS1248 16 times magnification, 40SPS.
Atmega16
- 基于ATMEGA16的数字倍频计电路加Proteus的仿真-Based on a ATMEGA16 the digital multiplier meter circuit plus Proteus simulation
fft
- FFT三分之一倍频程音频声强分析，从.wav文件中读取数据，计算34个频程段的声强值输出。-FFT one-third octave sound presser level analysis
pll
- 430单片机的锁相环技术，通过调节锁相环的倍频系数来调节单片机运行速度-The phase-locked loop technology 430 singlechip, through the multiplier factor regulating phase-locked loop to regulate the microcontroller running speed
decimal_test
- 用verilog编写的二倍频抽取程序，并包含了一个test文件，方便大家测试用。-The second harmonic extracting written in verilog
DDS-ADI
- DDS开发基本原理 基于查询相位的倍频器-DDS to develop basic principle is based on the query phase frequency multiplier
onethirdOB
- 用于计算振动噪声信号中的噪声信号的三分之一倍频程的计算-For the calculation of the one-third octave noise signal in the calculation of noise and vibration signal
test
- dac900驱动，使其产生正弦波，其中关于ram的查询以及pll倍频模块，该代码只是总的调用-DAC900 driver to produce a sine wave, which RAM query and PLL multiplier module, the code is just the total number of calls
verilog-pll
- 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL
OFDM
- 首先根据短训练字的特性进行相关运算，进行信号到达检测，当检测到相关值大于门限一定次数后，认为有信号到达。然后根据长训练字的特性，进行相关运算，进行OFDM符号FFT窗口起始位置的估计。估计出FFT窗口的位置后，先在时域进行小频偏的估计，将两个长训练字进行小频偏补偿后，进行FFT运算，根据FFT运算的结果进行整数倍频偏的估计。这些参数估计完成后，就可以进行数据解调了。先对数据部分进行完整的频偏补偿，然后根据估计的FFT窗口位置进行FFT运算得到频域的数据，进行解调。然后在对应于导频的子载波位置上提
test
- msp430f5529的时钟配置，倍频到16M，稳定工作-failed to translate
03.MCF5225X_PLL-----
- 飞思卡尔mcf52255锁相环,倍频80M，可自己更改-the pll about freecale mcf5255，you can choose the times you need
oct1-3matlab
- 1/3倍频程matlab 倍频程分析形成图像-1/3 octave octave analysis matlab image is formed
dcm-multiplier-routines-
- dcm倍频例程及其用法。包含完整的dcm工程文件。具体代码内容请下载查看-dcm multiplier routines and their usage. Dcm file contains the complete works. Please see the specific code download
PLL_test
- 基于DSP6713，对DSP内的锁相环相关的寄存器进行设置，实现锁相环倍频功能，DSP入门级资料。-Based on the DSP6713, the DSP phase-locked loops in the relevant register set, realization of PLL frequency multiplier function, DSP entry-level data.
74HC595--SPI-used-LED
- stm32通过spi口与74hc595相连，然后由74hc595控制8盏灯的闪灭，注意该工程所用外接高速晶振为12MHZ,而大部分板子为8M赫兹，使用时需要修改锁相环倍频系数。-stm32 through spi port is connected with 74hc595 and eight lights are ocontrolled by the 74hc595 , note that works with an external high-speed oscillator is 12M