搜索资源列表
rgb2yuv1
- 这个主要是实现RGB和YUV两种色彩空间的转换，其中用到的主要思想是，verilog语言中的浮点乘法怎么运算，流水线的思想。-This is achieved mainly two kinds of RGB and YUV color space conversion, which uses the main idea is, verilog language how floating point multiplication operations, lines of thought.
FFT_verilog
- verilog 实现的FFT 流水线操作，速度能达到200M-verilog pipelining the FFT implementation, the speed can reach 200M
FPGA.rar
- 流水线技术在FPGA设计中的应用 pdf ,Pipelining Technology in FPGA Design
waterline_adder.rar
- 这是一个用Verilog编写的四级流水线加法器,This is a Verilog prepared with four pipeline adder
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
56620_Part2_L2
- bcm公司讲解L2转发流程的文档，对学习二层转发及微码流水线设计有一定参考价值-bcm L2 forwarding
aco
- 对蚁群算法进行了改进用于解决零空闲流水线调度问题。-Improved ant colony algorithm for solving zero-idle flow shop problem.
GATest
- 求VC++基于遗传算法的流水线车间调度问题-Seeking VC++ Lines based on genetic algorithm-Shop Scheduling Problem
FFT
- 流水线模数转换电路输出信号做fft后求SNR,SNDR的matlab程序-matlab fft program for SNR and SNDR of pipelined analog to digital converter（ADC）
Pipeline
- java写的关于流水线工作过程的模拟程序-java to write the work on the assembly line process simulation program
median-filter
- 基于FPGA的图像中值滤波算法的优化及实现vhdl-中值滤波 利用VHDL语言实现三级流水线中值滤波-FPGA-based image filtering algorithm optimization and realization of vhdl-median filter using VHDL language three pipelined median filter
Senior-Advanced-FPGA-design
- FPGA设计高级进阶，讲述了流水线，乒乓操作，异步时钟域处理，状态机等内容-Senior Advanced FPGA design, about the line, ping-pong operation, asynchronous clock domain processing, state machine, etc.
mips
- 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
DirectX
- 一系列关于DirectX的学习资料，包括初始化，光照，纹理映射，绘制流水线等的ppt资料及源码-Series of DirectX, learning materials, including initialization, lighting, texture mapping, drawing lines and other information and source of ppt
FPGA-design-ideas-and-techniques
- FPGA 设计的四种常用思想与技巧包括：乒乓操作，流水线操作，串并转换技巧，数据接口同步方法-The four commonly used FPGA design ideas and techniques include: ping-pong operation, pipelining, and convert the string technique, synchronous data interface methods
SNDR-test-for-pipelined-ADC
- 流水线ADC信噪比测试程序,最后一级flash位数可调，可进行SNDR和SFDR的测试-SNDR test for pipelined ADC
fpga_FILTER
- 基于FPGA的可编程数字滤波器系统,基于FPGA的数字滤波器的设计与实现,基于FPGA流水线分布式算法的FIR滤波器的实现-FPGA-based programmable digital filter system, the digital filter based on FPGA Design and Implementation, Distributed Pipelined FPGA-based FIR filter algorithm to achieve
interweave_1
- 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by colu
CORDIC
- ：CORDIC算法将复杂的算术运算转化为简单的加法和移位操作，然后逐次逼近结果。这种方法很好的兼顾了精度、速度和硬件复杂度，它与VLSI技术的结合对DSP算法的硬件实现具有极大的意义，因而在数字信号处理领域得到了广泛应用。本文首先简要介绍了CORDIC算法的原理，然后详细描述了双模式（旋转/向量）CORDIC算法的预处理和后处理，并且基于FPGA实现了流水线双模CORDIC算法。-By converting complex arithmetic into simple operations su