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16-bit数的偶数奇偶校验
- 16-bit数的偶数奇偶校验及阶乘运算，用verilog写-16-bit number of even parity and factorial computation, written using Verilog
space-phase-modulation-based-on-8-bit-microprocess
- 这是基于78k0八位微控制器的空间相位调制技术介绍以及主体程序-78k0 which is based on 8-bit microcontroller space phase modulation technology presentations and the main procedure
Bit-Error-RateSimulationUsingMatlab
- Matlab is an ideal tool for simulating digital communications systems, thanks to its easy scr ipting language and excellent data visualization capabilities. One of the most frequent simulation tasks in the field of digital communications is bit-e
signed four bit multiplier
- a multiplier for four bit binary number
SOA Cloth Simulation with 256-bit Intel Advanced Vector Extensions (Intel AVX)
- This article describes a code sample that uses the Intel® Advanced Vector Extensions (Intel® AVX) for computing mesh-based cloth simulation. A structure of arrays (SOA) implementation is used to maximize data parallelism enabling the usage of 256-bit
Samsung 8G x 8 Bit NAND Flash Memory SPEC & Simulatiom model
- Samsung 8G x 8 Bit NAND Flash Memory SPEC and verilog Simulatiom model
三种16位整数运算器的ALU设计方法
- 三种16位整数运算器的ALU设计方法，调用库函数74181（4位ALU），组成串行16位运算器。(用74181的正逻辑) B．调用库函数74181和74182，组成提前进位16位运算器。(用74181的正逻辑) 注意：调74181库设计，加进位是“0”有效，减借位是“1”有效，所以最高位进位或借位标志寄存器要统一调整到高有效 C．用always @，case方式描述16位运算器。,Three 16-bit integer arithmetic logic unit of the ALU
Decimal--format-32-bit-IEE754 十进制转化32位IEE754浮点格式函数
- 十进制转化32位IEE754浮点格式函数，32位IEE754浮点格式函数转化十进制-Decimal floating point format conversion function 32-bit IEE754, 32 IEE754 decimal floating point format conversion function
bpsk.rar
- 用C++实现BPSK的仿真，包括信源，调制，信道，解调，计算误比特率,Using C++ implementation BPSK simulation, including source, modulation, channel, demodulator, bit error rate calculation
BER.rar
- OFDM，MPSK，MDPSK,QAM四种调制方式误比特率的matlab仿真代码。,Matlab simulation code of OFDM, MPSK, MDPSK, QAM modulation bit error rate
baud-rate-and-bit-rate
- 波特率与比特率的区别，介绍得很详细-baud rate and bit rate comparation
使用verilog hdl实现16位的cpu设计
- 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！,To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
RISC8.ZIP
- verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
74096190ziyuanfenpei1
- 对OFDM系统进行自适应分配，主要对子载波，比特和功率进行分配，已达到降低发射端功率的目标。-Adaptive Allocation for OFDM systems, the main pair carrier, bit, and power distribution, has reached the goal of reducing the transmitter power.
7bitcoding
- PDU 7BIT编码程序，目前，发送短消息常用Text和PDU(Protocol Data Unit，协议数据单元)模式。使用Text模式收发短信代码简单，实现起来十分容易，但最大的缺点是不能收发中文短信；而PDU模式不仅支持中文短信，也能发送英文短信。PDU模式收发短信可以使用3种编码：7-bit、8-bit和UCS2编码。7-bit编码用于发送普通的ASCII字符，8-bit编码通常用于发送数据消息，UCS2编码用于发送Unicode字符。-PDU 7BIT encoding process
Booth_mult
- Booth multiplier for multiplication of 2 bit binary nos.
tasm32
- 32位汇编语言编译器，学习汇编语言的必备工具。-32-bit assembly language compiler, an indispensable tool for learning assembly language.
uwb
- 超宽带高斯脉冲的源代码，包括波形分析和误码率计算-Ultra-wideband Gaussian pulse source code, including waveform analysis and bit error rate calculation
16bit-CLA
- 16 bit carry look ahead adder verilog code