搜索资源列表
booth_wallace_multiplier.
- booth wallance tree which is mathematical execution of code.
test_bench
- test bench for booth multiplier
Radix-2
- Radix2 booth multiplier
BOOTH2
- verilog booh multiplier-booth
Vision-Tec-BD
- VisionTec 16 Digit Booth Display Hex File copy from Working Hardware. Test and Run Ok. Manoj Soorya
SEQ_MULT
- SEQUENTIAL MULTIPLIER IN VERILOG USING BOOTH S ALGORITHM
snap3
- 火车站的售票口、进站口、出站口都是旅客必经之地，在这些地方旅客的行动速度就会适当放慢，这样为人脸比对识别提供了有利的条件。一般相关部门会在售票处和进出站口安装录像监控设备，人工辨认方式进行脸部识别.-Station ticket booth, pit mouth, the station is travelers must pass through in these local action will be appropriate to slow down the speed of travel
multer
- 16*16位的乘法器，用booth编码，采用Wallace树结构，用超前进位加法器。-booth encoded multiplier
Android-Photo-Booth-master
- 在android手机或者平板电脑上，在Camera预览上应用实时的特效-Apply Live Effects to the Camera preview on android phones and tablets.
17
- 网上淘书吧 （1）本系统分为前后台管理。前台主要包括图书展台、网上调查、购物车、收银台、会员管理、订单查询等内容。 （2）用户登录系统后，可进入系统后台，在系统后台中可实现图书管理、用户管理、订单管理、公告管理、投票管理等。 （3）系统后台还提供了退出系统超链接。 -Online Taoshu it- (1) The system is divided into front and back office management. Reception includes books bo
booth_multiplie_module
- 利用verilog实现的Booth算法乘法器，对想学习乘法器的将会有很大的帮助.-Booth algorithm verilog realization use multipliers, the multiplier will want to learn a great help.
4booth_multiplie_module_2
- 采用Verilog对Booth算法乘法器的改进，对想学习乘法器的会有很大的帮助。-Improved algorithm using Verilog Booth multiplier, multiplier want to learn to have a lot of help.
Booth4b
- booth 4 bits programmed by verilog and simulated using ISE software and no implemented
32bit_multiply
- 包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。-Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementat
eetop.cn_Booth_mutipler_v2
- 新型32位booth乘法器的实现,使用verilog的一种新型乘法器改进实现-The new 32 booth multiplier implementations
booth123
- booth multiplication is one of the modern and fastest method to multilply, we propose this code for designer to have more elaborated code in this field
boooth--MUL
- this code provides you one of the most perfect codes to design a booth multiplier and corresopnding test bench
booth147
- this code provides you a perfect and exccelent code to desgin a booth multiplier
cmp42
- 用于乘法器设计，8位Booth译码乘法器，4-2压缩结构，加速乘法运算速度-Used for the design of multiplier, 8 Booth decoding multiplier, 4-2 compressed structure, accelerate the multiplication rate
Booth2_final
- 该文件是booth乘法器的verilog源代码，经过最终的仿真，可以直接运行-This file is booth multiplier verilog code, after the final simulation, can be directly run