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baweichufaqi
- 介绍了利用VHDL实现八位除法,采用层次化设计,该除法器采用了VHDL的混合输入方式,将除法器分成若干个子模块后,对各个子模块分别设计,各自生成功能模块完成整体设计,实现了任意八位无符号数的除法。 -Introduced the use of VHDL to achieve eight division, the use of hierarchical design, the divider using VHDL mixed-input methods, will be divided in
dzq
- 利用数控分频器设计硬件电子琴.硬件电子琴电路模块设计-Use hardware organ NC divider design. Hardware electric circuit module design
divide
- Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
15
- 半整数分频器的设计 请不要上传有版权争议的内容和木马病毒代码 -Half-integer divider design, please do not upload copyrighted content and controversial Trojan code
ps
- RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua
Example1
- 本例展示了如何利用外设TIM2来产生四路频率不同的信号。 TIM2时钟设置为36MHz，预分频设置为2，使用输出比较-翻转模式（Output Compare Toggle Mode）。 TIM2计数器时钟可表达为：TIM2 counter clock = TIMxCLK / (Prescaler +1) = 12 MHz 设置TIM2_CCR1寄存器值为32768，则CC1更新频率为TIM2计数器时钟频率除以CCR1寄存器值，为366.2 Hz。因此，TIM2通道1
dividend4
- 本设计是一个八位被除数除以四位除数，得到不超过四位的商的整数除法器。被除数、除数、商和余数都是无符号整数。-The design is an eight dividend divided by the divisor of four, to be not more than 4 business integer divider. Dividend, divisor, and remainder are unsigned integers.
shuzizhongdianlu
- 利用计数器和分频器设计一个实时的时钟。一共需要1个模24计数器、2个模6计数器、2个模10计数器、一个生成1Hz的分频器和6个数码管解码器。最终用HEX5~HEX4显示小时（0~23），用HEX3~HEX2显示分钟（0~59），用HEX1~HEX0显示秒钟（0~59）。 -The use of counters and prescaler design a real-time clock. Mold needs a total of 24 counters, 2 Die 6 counters,
chfadianlubianma
- 除法电路编码，用于生成（63，57）循环码-Divider circuit encoding, used to generate (63,57) cyclic code
fpga_div
- Altera的FPGA，设计的硬件除法器-Altera' s FPGA, the design of the hardware divider
divp5
- fpga上实现的最小是0.5分频的任意分频器-FPGA to achieve the minimum 0.5 hours are arbitrary frequency divider
measurefrequence
- 本系统采用51单片机和一些用做分频器的数字芯片，用液晶显示频率值。可以精确到小数点后两位，响应时间短。-The system uses a single-chip microcomputer 51 and some used to do figure divider chips, liquid crystal display with frequency value. Can be accurate to two decimal places, a short response time.
phase_div
- 相位分频器源代码，正确，测试通过-Phase divider source code, correct, test
vhdl-devider
- 基于vhdl的分频器设计，分频器在数字系统设计中应用频繁-VHDL-based design of the divider, divider in the digital system design applications frequently
clk4
- clk4 时钟分频设计用于FPGA入门设计-clk4 clock divider is designed for FPGA design entry
adc
- This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assuming a 30Mhz XCLKIN). The clock divider in the ADC is not used so that the ADC will see the 25Mhz on the HSPCLK. Interrupts are enabled and the EVA i
nfenpin
- N分频器则是一个简单的除N 计数器。分频器对脉冲加减电路的输出脉冲再进行N分频，得到整个环路的输出信号Fout。-N divider is a simple addition to N counter. Addition and subtraction of the pulse divider circuit output pulse frequency N again, the whole loop of the output signal Fout.
fenping
- 介绍了各种分频器的设计，VHDL描述。包括偶数分频器，奇数分频器，办整数分频器-Introduce the design of a variety of crossovers, VHDL descr iption. Including even-numbered divider, prescaler odd, do integer divider
fq_div
- 一种实现任意整数分频的ＶＨＤＬ源代码，已经经过调试-Achieve an arbitrary integer divider of the VHDL source code, has been testing
clk_div
- VHDL描述的时钟分频电路，用途广-VHDL descr iption of the clock divider circuit, uses widely ...