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- 采集0-7路输入来自直流源经分压器产生的0～5 V直流电压（可功能扩展，8路可接不同的传感器，采集不同的信号,例如:温度、湿度、图象、声音等）ADC0809将各路模拟信号分别转换成8位二进制数字信号,再对各路数据进行显示。各路通道采集方式为以约5s为周期循环采集（即0路、1路……7路、0路…）约每5ms更新，重新采集一次。显示方式为循环显示和单路显示：开关打开时，循环显示0-7路采集的数据；开关闭合时，显示当前单路采集的数据。3个七段数码管显示结果:最左边的一个数码管DS0显示通道号，其它两个数
FREDIV
- 无限分频器,VHDL编写，可以实现奇数和偶数分频。-Unlimited divider, VHDL development, can be odd and even frequency.
frequency
- frequency divider circuit divides the input frequency (clk) by various factors
divhalf
- 本分频器不仅可以达到任意的整数分频，还可以达到半分频，例如3.5分频-The divider can be achieved not only arbitrary integer frequency, but also semi-sub-band can be achieved, for example, frequency of 3.5 points
divider
- a pakage containing three diferent dividers and comparing them
FPQ
- 基于FPGA的数控分频器，可以吧一个时钟信号分成不同频率的时钟信号。-FPGA-based digital frequency divider, a clock signal can now be divided into different frequency clock signals.
clk_gen
- 基于fpga的分频器的vhdl描述，可以直接调用，只需修改一些参数-Fpga based on the divider vhdl descr iption, can be directly called, simply changing some parameters
fast_divider
- 快速除法器，采用循环移位相减算法。 已经通过仿真。-Quick divider using cyclic shift subtraction algorithm. Simulation has been passed.
T0offenpin
- 分频器的设计。基于M16.用T0定时器。有proteus仿真-Divider design. Based on the M16. By T0 timer. There proteus simulation
Modelsim_fredevider_testbench_TEXTIO
- 此文档通过分频器的例子描述了如何使用modelsim，如何编写testbench以及textio的使用-This document is an example through the divider describes how to use the modelsim, how to write a testbench and use textio
book_divider
- 文本分割 把文件与程序放在同一文件夹下 启动程序后 在程序中输入该文件名（要有后缀），然后输入你想分成几部分 即可完成分割。-file divider，please put the programme with the file you wanna divide in the same folder.after you run the programme ,please input the name of the file,then input the number to which you
clk_gen
- 基于vhdl的分频器模块设计，已经经过调试，可直接调用-Divider vhdl module based on the design, debugging has been directly call
diverse
- 该pdf 详细介绍了 提高除法电路的方法。和设计出发电路时要注意的问题， 介绍了各种除法设计代码-Pdf details the divider circuit to improve the method. And design of the starting circuit should pay attention to the issue of when to introduce a variety of design code division
fenpinqi
- verilog写的分频器，其最高频率为输入频率，没毛刺，挺好-written in verilog divider, the maximum frequency of input frequency, no glitches, very good
divid
- 一个ISE下的简单分频器设计，通过led显示设计结果-Under a simple divider ISE design, through design led display
divclock
- 基于VHDL的各种分频器的设计。很好用，可修改成各种通用分频器-VHDL-based design of the various divider. Very good, and can be modified into a variety of common divider
simpleDivider
- Divider，VHDL语言，硬件描述语言源码-Divider, VHDL language, VHDL source code
shuzishiboqi
- 分频器，这是一个特殊的分频器。有不同的频率。可以选择。-Divider, which is a special divider. Have different frequencies. To choose from.
Freq_Divider
- frequency divider fpga get slow frequency
VHDL
- 基于vhdl数控分频器的设计与应用，少有的关于分频方法的介绍-Divider based on vhdl design and application of NC