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multiplieranddivider
- 乘法器和除法器的VHDL实现方法,可运行,占用逻辑资源少。-VHDL descritpion about muiltiplier and divider
Verilog-HDL
- 本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路,利用数控分频的原理设计乐曲硬件演奏电路,并定制LPM-ROM存储音乐数据,-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing ha
Frequency_divider
- 奇数分频器,通用分频器,占空比1:1分频器, 占空比非1:1分频器-Frequency divider
Clk50M_div_1HZ
- 分频实验,将50M时钟分频为1HZ,输出LED1,闪亮-Crossover experiments, 50M clock divider is 1HZ, output LED1, shiny
practise
- FPGA实验板设计一个数字跑表。根据题目要求利用VHDL语言设计出一个系统,包括分频器,开关消抖,使能控制,计数器,锁存器,数据选择器及显示译码器。-FPGA experimental board design a digital stopwatch. According to subject the use of VHDL language to design a system, including the divider, switch debounce, enable control, c
Sampling-PCB
- 电压、电流及漏电的采样电路,由整流、分压、滤波等功能电路组成。-Voltage, current and the drain of the sampling circuit, the rectified voltage divider, the filter circuit, and other functions.
fec_code
- The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by four, but the divide value can be chan
multiplier-ROM--FIFO-memory
- 布斯,阵列乘法器,加减交替除法器,以及ROM存储器,FIFO存储器-Booth, array multiplier, divider alternately add and subtract, and ROM memory, FIFO memory
fenpinqi
- 基于vhdl语言编写的分频器程序,可实现五十分频。-Based divider vhdl language program, can achieve five very frequently.
Sequence-Detector
- 利用状态机设计一个序列检测器,用以检测“1101”。用btn[1]和btn[0]作为输入分别代表1和0,输入的当前数字显示在数码管最后一位,每当新输入一个数字,之前输入的数字左移一位,依次显示出最近输入的四位数字,无输入时数码管不显示任何数字。clk时钟需要分频后才可作为检测时钟(建议分频至190Hz),每当检测到序列中有“1101”出现时,led[0]点亮,即数码显示管上显示“1101”时led[0]点亮;当按下btn[2]时恢复初始状态。-The use of a state machine
Four-bit-signed-number-division
- 设计四位定点有符号整数除法器(op=ai÷bi),软件仿真通过后下载到FPGA板子进行验证 [具体要求] 1、 使用clock为输入时钟信号,其频率为50MHz 2、 使用拨码开关sw7~sw4为被除数ai,其中sw7为MSB(高位),sw4为LSB(低位) 3、 使用拨码开关sw3~sw0为除数bi,其中sw3为MSB,sw0为LSB 4、 使用按钮btn<0>作为输入确定信号,在每次改变输入时按下按钮得到输出结果 5、 以LED7~4为所得商op,LED3
clk-divider
- linux sound pxa2xx-ac97.c AC97 support for the Intel PXA2xx chip. -linux sound pxa2xx-ac97.c AC97 support for the Intel PXA2xx chip.
Proj2_final
- 2 4 8级流水线乘法器 以及 除法器 包括makefile 和 tcl 比较详细-248 stage pipeline multiplier and divider includes more detailed makefile and tcl
clk
- This fixups the register CCM_CSCMR1 write value. The write read divider values of the aclk_podf field of that register have the relationship described by the following table:.
FPGA__source-code__Verilog
- FPGA部分基础功能源代码,适合初学者进行学习仿真,代码可读性强,通俗易懂,逻辑清晰。包括触发器,全加器,分频,并串转换,计数器,序列发生器等Verilog语言源代码。- Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Includ
mouse_kit
- 实现难度可调(6级,速度不同)的简单打地鼠游戏。开发板上的led灯代表地鼠,按键代表锤子。此程序代码可直接执行,适合初学者VHDL入门。 源码中,divider为分屏器;key_scan为按键扫描;random产生随机数;music为背景音乐播放模块;manage为主程序模块。-Adjustable implementation difficulty (6 level, different speeds) simple whack-a-mole game.The led lights on
VHDL-projects
- I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
div
- 10进制分频器,可通过简单修改代码实现任意进制的分频,简单有效-decimal divider
clk-divide5
- 实现5分频计数的veriog电路,简单易懂,欢迎大家下载学习-Achieve 5 divider count veriog circuit, easy to understand, welcome to download the study
cntr_4bit
- This the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit-This is the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit