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convcode_interleaving.rar
- 一个实现了213卷积码编码和卷积交织的verilog程序，编译通过,An implementation of 213 convlution code and interleaving on verilog HDL.
verilog
- 基于FPGA的LCD12864驱动显示程序 verilog hdl编译已通过 -LCD12864 Show verilog hdl compiler
SPI_Master
- verilog HDL 语言描述的8位并行转SPI程序-verilog HDL language descr iption of the 8-bit parallel transfer SPI program
Verilog-to-do-SD-card
- 本文档内是基于Verilog HDL的SD卡SPI模式下的读写程序，内有详细的注释，且通俗易懂。-This document is based on Verilog HDL in the SD card in SPI mode to read and write procedures, which are detailed notes, and easy to understand.
PID
- 用Verilog HDL编写的PID程序代码，成功调试，运行良好。-The source code of PID in Verilog HDL.Simulation was successful.
EEPROM_RD_WR.rar
- 本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。,This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (e
Verilog.rar
- verilog HDL 4×4矩阵键盘驱动程序包括硬件电路图,verilog
IDCT
- 用verilog HDL语言编写的IDCT程序，可以计算8*8的整形数矩阵，用ISE 9.1i编译通过-Using verilog HDL language of the IDCT program can calculate the number of 8* 8 matrix of plastic, with ISE 9.1i compiled by
ps2_mouse_interface
- ps2接口的鼠标与vga接口的驱动程序，Verilog HDL语言，运用于FPGA-ps2_mouse_interface and vga in Verilog HDL language, applied to FPGA
Verilog
- 是摩托罗拉关于Verilog HDL的开发规范，相信对于学习Verilog程序设计的人会有很大的帮助-Motorola on the development of Verilog HDL specification, I believe that learning Verilog for programming will be of great help to people
dds
- 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
pal_vedio
- 基于FPGA的pal制模拟视频显示程序，verilog Hdl-pal-d vedio display fpga verilog
d_e_g_dds
- 基于Verilog HDL的迟早门码元同步方案中的DDS程序，已经仿真通过，可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. F
VerilogHDL
- 用Verilog HDL语言编写的跑马灯小程序，可直接在FPGA上运行-With the Verilog HDL language of the Marquee applet can be run directly on the FPGA
SOPC_pwm_source
- 在SOPC下制作自定义部件（PWM发生器）的源程序，包括硬件描述HDL文件和驱动程序文件-Produced in the SOPC custom component (PWM generator) of the source, including hardware descr iption HDL files and driver files
jsq
- 本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.
PCR
- 本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。-This procedure is in the transport stream during transmission of program the clock to carry out field testing and modification, using Verilog HDL language programming.
yima3_8
- 译码是编码的逆过程，它的功能是将具有特定含义的二进制码进行辨别，并转换成控制信号。此程序虽然简单，但能很好的理解用eril HDL语言设计组合逻辑电路的过程。-Decoding is the inverse process of encoding, and its function is to have a specific meaning to distinguish between binary code and converted into control signals. Althoug
VGA_driver_verilog
- 基于Verilog HDL的VGA驱动程序设计-Based on Verilog HDL design of the VGA driver
verilog_led
- 基于Verilog HDL的数码管程序设计-Verilog HDL-based digital control programming