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JMUX2TO1_vhdl
- This source are usefull function in VHDL for Transfer MCU Data betwine FPGA 2 port 8bit s wide Mux -This source are usefull function in VHDL for Transfer MCU Data betwine FPGA 2 port 8bit s wide Mux
mux
- 数据选择器，可移植性很强，适合很多程序中使用，非常好！简单-Data selector, portability is very strong, suitable for use in many procedures, very good! simple
demo13-mux_vhdl
- vhdl demo of mux using altera board
fet410_lcd_03
- msp430f425的LCD驱动程序，4-mux模式-MSP-FET430P410 Demo- LCD, Display Numbers on a 4-Mux LCD // // Descr iption: This program displays digits stored in the variable "value" // on a 4-mux LCD, then waits in low power mode 3. To use the program run it
Mixer_SampleProject
- Cypress PSoC3,5 example using internal analog-mux, analog + digital blocks
Filter_SampleProject
- Anaog filters and analog mux used internaly PSoC3,5
Behavioral-Modeling
- A Code that illustrates 12 bit switch, 2x1 Mux, 2x4 Decoder in behavioral modeling in Verilog HDL using modelsim IDE
datasheet
- PI3L110 Quad mux/demux
twomux4to1
- this source is 4to1 mux two design. verilog source.
report
- vhdl code for basic gates, adders, subtractors , MUX and Demux
Mux
- designing of multiplexer using vhdl language
Based-on-DSP48X-FIR-Design
- 基于DSP48X的FIR的设计，实验中用到的所有完整的工程文件在文件夹下: （1）非对称滤波器的设计，完整的工程文件包含： asymmetric_8weight.mdl （2）对称滤波器的设计，完整的工程文件包含： even_symmetric_8.mdl odd_symmetric_9.mdl （3）多路复用滤波器的设计，完整的工程文件包含： mux_2channels.mdl mux_3channels.mdl mux_2channels_pipelined.mdl-Bas
mux16
- mux 乘法器 verilog ise xilinx-the mux multiplier Verilog ise xilinx
MUXER
- SHOWS THE SIMPLEST WAY TO CREATE A SIMPLE MUX IN VHDL-SHOWS THE SIMPLEST WAY TO CREATE A SIMPLE MUX IN VHDL...
verilog-code
- 都是verilog代码：多路选择器代码，储存器代码，时钟分频器代码，串并转换电路代码，香农扩展运算代码，ram代码。-MUX code and REGISTER code clock divider code string conversion circuit code, Shannon extended op code, the ram code.
mux_case
- 用case 语句描述的4 选1 MUX源代码程序实现-case4（1） ，VHDL&verilog
mux_v
- a 4 bit mux vhdl code
mux
- multiplixer generic for vhdl
TsToFlv
- 解析TS文件，获取音视频数据和相关信息，并转换为FLV封装格式-Demux ts stream, get Audio & Video data,then mux to flv file
a1
- 1 bit MUX 用ISE写的1bit MUX的verilog code 可以在ISE上模拟1bit MUX的运作-1 bit MUX It is a file of verilog code to design a 1 bit MUX. It is design by ISEbit