搜索资源列表
mux4_to_1
- this files in quartus2 are 4 to 1 mux
fulladd
- this files in Quartus2 are fulladder
jichunqi
- 8位寄存器，quartus2软件下编写的vhdl文件-8-bit register, vhdl language, quartus2 software write down.
quartus2design
- 一个介绍quartus2设计方法和步骤的文档，比较适合初学者进行学习使用。-An introduction quartus2 design methods and steps of document, suitable for beginners learning to use.
ADC0804
- 使用Altera公司芯片编写的在quartus2下的verliog程序，改程序为DA芯片ADC0804的驱动，并将采样值现实在数码管上。程序模块化，可直接调用。-Using the Altera chip prepared under the quartus2 verliog program, change the program for the DA chip ADC0804 driver, and the sampling value of the reality in the digita
decoder38-ok-38译码器
- 使用quartus2软件的VHDL编写了简单38译码器，希望大家能积极学习(The use of quartus2 software VHDL prepared a simple 38 decoder, I hope we can actively study)
mux16
- 用verilog写的乘法器，在quartus里可以直接运行，有详细注释(Multiplier written in Verilog, in quartus can run directly, with detailed notes)
Exp302
- 这是一个在quartus2上写好的JK触发器，下载并运行其中quartus文件即可。(This is a JK trigger written on quartus2, downloading and running the quartus file.)
vhdl译码显示器设计
- vhdl译码显示器设计，用quartus2软件编写，可实现数码管的显示译码功能。(VHDL decipher display design, written in quartus2 software, can realize the display and decoding function of the digital tube.)
CPLD-FREQUENCY CONTROL
- 通过手动和自动方式对输出频率进行设置，通过锁相环输出。(The output frequency is set by manual and automatic mode, and output by the phase locked loop.)
counter_60
- 利用EDA的Quartus2语言，实现时分秒的时钟计时等功能。(The use of EDA Quartus2 language, and the clock timer function realization.)
mux41
- 利用EDA的Quartus2语言，实现四进一出的译码等功能。(Using the Quartus2 language of EDA, the function of decoding the four into one is realized.)
quartus yima_38
- 利用EDA的Quartus2语言，实现三进八出的译码等功能。(The use of EDA Quartus2 language, to achieve three out of the eight decoding function.)
fp
- 通过quartus2软件使用VHDL语言将输入频率分频的程序(divide the frequency)
Exp301
- 这是一个D锁存器完整文件，打开quartus2运行即可(This is a complete file of the D latch, open the quartus2 to run)
chuankou
- UART loopback测试实例，接收PC端发送的UART数据，原数据返回给PC端，即loopback功能 可用FPGA开发板验证(The UART loopback test example receives the UART data sent by the PC terminal, and the original data is returned to the PC terminal, that is, the loopback function.)
FPGA乐曲演奏电路
- 乐曲硬件演奏电路设计,采用verilog-VHDL语言编写，使用quartus2开发平台编译仿真(design of music hardware performance circuit(verilogVHDL))
分频
- 最简单的分频设计，包含quartus2和ise两种
elevator
- de2-115开发板2人6层电梯Verilog语言实现(Verilog language implementation of de2-115 development board 2-person 6-layer elevator)