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exercise3
- 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
VGA800
- 本代码用verilog语言，配合quartus里自带的fifo来简单实现vga显示屏的操作，重点在于弄清楚时序。代码中被注释的部分也可以用于彩色条纹的测试。-The code to use verilog language, with quartus in fifo comes to simply achieve vga screen operation, with emphasis on clear timing. The code portion of the notes can be te
uartfifo
- 一个基于verilog的fifo的例子，由数据产生模块产生数据传到fifo中，然后同过发送模块将数据发到上位机上。-One based on the fifo verilog example, by the data generation module generates data to the fifo, and then sent over the same module sends data to the host computer.
ht_fifo
- fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
20131010-code
- fx2lp 68013 xilinx XC3s400 实现slave fifo通讯，包括68013的固件以及fpga的代码（verilog）。摸了好久才调试通过的，特共享出来解救苍生！-fx2lp 68013 xilinx XC3s400 slave fifo
uart_fifo
- 带fifo的串口通信verilog设计，该设计为学习uart所用，完成PC端发送至fpga后fpga原数据返回，支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
async_pulse
- asynchronous fifo with pulse input write by verilog code
synchoronous_FIFO(jianban)
- 基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit，深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
fifo_datapath
- verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
t4_fifo
- FIFO的verilog与VHDL的实现，并与FIFO的IP核做对比，为了方便大家学习，每个文件均附有测试脚本文件，希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test scr ipt file, we want to be useful.
vga_pannel_design
- verilog代码写的控制vga显示的实例，利用状态机进行描述，很好的参考例子-verilog language write serial fifo instance, because the serial port speed is relatively slow, a lot of the interface will use fifo buffer
I2S
- 本代码提供一种音频I2S读取数据的verilog代码，并且向fifo写入-This code provides an I2S audio data is read verilog code, and write to the fifo
fifo2
- 异步fifo 先进先出 用于缓冲数据，用verilog HDL所写，在quartus II中测试通过，modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
fifo_datapath
- verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
SRAM_WR
- 本人自己经过实践检验的SRAM读写器，用Verilog编写的，可以作为FIFO使用。-I own proven SRAM reader, using Verilog prepared, can be used as a FIFO.
New_UART_verilog
- 这个是最新的UART的verilog代码，里边含有和UART相关的所有function,比如状态机，接收发送FIFO等相关代码。-New UART verilog sample code,Include FIFO code state mashine code ,recevier/trasmiter code
FIFO--verilog
- 同步jk触发器 实现10进制 简单易懂-jk