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8051IPcore,verilogHDL实现
- 用verilog写的很好的cpu core-using Verilog write a good cpu core
VerilogHDL
- Verilog HDL程序,对硬件开发有兴趣或需要的朋友赶快down下来-Verilog HDL procedures, the development of hardware are interested or needs a friend to see down quickly down
CAN协议控制器的Verilog实现
- 基于FPGA的CAN总线控制器,VERILOGHDL源代码,Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
veriloghdl快速入门
- verilog hdl 快速入门,里面包含很多有用的硬件描述语言的程序-Verilog HDL Quick Start, which contains many useful hardware descr iption language procedures
cardPhone
- 卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能-card billing telephone circuits, verilogHDL prepared with the major simulate the real phone function
RISC Core_verilog
- RISC的指令VerilogHDL实现-RISC instructions to achieve VerilogHDL
crcDecode
- 比较完善的CRC编码VerilogHDL描述-more perfect descr iption of CRC coding VerilogHDL
PAOBIAO_V
- 带音乐功能的跑表VerilogHDL描述-music with the stopwatch Verilog HDL descr iption
gatediscrip
- 各种门电路模型的VerilogHDL描述-various gates model of Verilog HDL descr iption
manydecoders_V
- 各种解码译码电路模型的VerilogHDL描述-various decoder decoding circuit model of Verilog HDL descr iption
VerilogHDLICdesign
- 精通VerilogHDL:IC设计核心技术实例详解-proficient VerilogHDL : IC design example explanation of the core technology
RSSI_contr
- VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage
VGA_2c5
- FPGA EP2C5 VGA 使用verilogHdl-VGA EP2C5 FPGA use verilogHdl
mod6_divide
- 用VerilogHDL编写的,一个占空比为50%的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit
de_mux
- 一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer
mod6_cnt
- 一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
mult8x8
- 一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
DSPBuilderFIR.files
- 在信息信号处理过程中,如对信号的过滤、检测、预测等,都要使用滤波器,数字滤波器是数字信号处理(DSP,DigitalSignalProcessing)中使用最广泛的一种器件。常用的滤波器有无限长单位脉冲响应(ⅡR)滤波器和有限长单位脉冲响应(FIR)滤波器两种[1],其中,FIR滤波器能提供理想的线性相位响应,在整个频带上获得常数群时延从而得到零失真输出信号,同时它可以采用十分简单的算法实现,这两个优点使FIR滤波器成为明智的设计工程师的首选,在采用VHDL或VerilogHDL等硬件描述语言设
VerilogHDL88
- veriloghdl语言工具书,适合初次了解cpld和fpga工程师学习使用-veriloghdl language tool, suitable for initial understanding of fpga and cpld engineers learning
FIRVerilogHDL
- it is a fir filter program VerilogHDL.-it is a filter program VerilogHDL fir.