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xapp460
- xilinx hdmi tx rx verilog code datasheet
xapp341
- verilog uart for spartan 3 fpga, its great
verilog_circuits
- describes the verilog code for logic circuits
verilog
- 讲述的是verilog HDL 的一些实际应用与联系。还宝库奥一些总结性的知识。-About the verilog HDL and contact some of the practical application. Treasure-house of Austria is also a number of conclusive knowledge.
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
i2c.tar
- i2c core for verilog hdl
i2c_customer_pack
- i2c core for verilog hdl
SDH
- FPGA的应用，数字交叉连接矩阵的应用，VERILOG的一些应用等-FPGA applications, the application of digital cross-connect matrix, VERILOG some of the applications
lcd1602verilog
- verilog lcd液晶1602驱动 这个程序的显示字符显示的是ASCII码，显示的数据由DB8输出到LCD上-verilog
Verilog
- Verilog tutorial file
can-verilog
- 汽车工业系统里面的电气设备常用的总线控制-Automotive systems commonly used in electrical equipment inside the bus control
VerilogHDL_tuxiang
- 介绍一种用于卫星姿态测量的CMOS图像敏感器--STAR250的时序驱动信号，并使用Verilog HDL语言设计驱动时序电路。经布线、仿真、测试后验证了驱动信号的正确性。 -Introduce a measurement for the satellite attitude CMOS image sensor- STAR250 timing drive signals, and use the Verilog HDL language design-driven sequential circ
BasedontheHDB3encoderverilogimplementation
- 基于verilog的HDB3编码器的实现-Based on the HDB3 encoder verilog implementation
FPGAEthernetVerilog
- 使用Verilog语言在FPGA平台上控制Ethernet上数据的发送与接收-FPGA realization using Verilog to control transmitting and receiving data over Ethernet
NewFolder2
- Verilog and VHDL programs for sipo buffer,d flip flop etc
avs_export
- the avalon verilog slave sram interface fron be micron
Lecture_Verilog_Synthesis
- It includes all techniques for optimization in verilog coding(pipelining, resource sharing, loop unrolling,...)
Lecture_Verification
- Writing testbench in verilog
Signed_Operations
- Signed operation in verilog
fifo
- this verilog program for sysnchronous FIFO ,this document contains some error using before correct and then use,-this is verilog program for sysnchronous FIFO ,this document contains some error using before correct and then use,