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大量verilog代码
- 大量verilog设计实例
Verilog HDL的基础教程
- Verilog HDL的基础教程PDF资料
AD转换.doc
- Verilog
verilog基本功
- verilog基本功---详细介绍verilog编码的基本规则，深入的讲解了一些难点和重点，非常适合初学者学习
Verilog代码编写规范
- 在一个项目组内部、一个项目的进程中，应该有一套类似的代码编写规范来作为约束。 总的方向是，努力写整洁、可读性好的代码
矩阵键盘 verilog
- 用verilog写的 矩阵键盘
verilog 代码编写规范
- verilog 代码编写规范
veilog HDL编码规范
- 详细介绍了verilog HDL编码的注意事项和基本规范。分为可综合部分，仿真专用部分以及nc-verilog仿真环境的建立。
xge_mac_latest.tar.gz
- Language - Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. ,Language- Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defin
cy7c68013工作在SLAVE FIFO下的FPGA源代码
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写,cy7c68013 slave fifo mode code ,written by hard ware language
设计与验证-Verilog HDL
- 设计与验证-Verilog HDL.rar
SPI-in-Verilog-implementation
- SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).
UART_spec
- a UART model with FIFO buffer, design with verilog
iic_master
- it is a iic source verilog code with its testcase which can act only as master
NonblockingAssignment
- 详细介绍verilog语言中的阻塞和非阻塞问题-Detailed Verilog language obstructive and non-blocking problem
async_transmitter
- 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
BasedontheHDB3encoderverilogimplementation
- 基于verilog的HDB3编码器的实现-Based on the HDB3 encoder verilog implementation
FPGAEthernetVerilog
- 使用Verilog语言在FPGA平台上控制Ethernet上数据的发送与接收-FPGA realization using Verilog to control transmitting and receiving data over Ethernet
IIC_slave_core
- iic 总线规范和多个iic Verilog的设计论文,均为pdf-pdf of verilog iic
Advanced Digital Design with the Verilog HDL
- Advanced Digital Design with the Verilog HDL (M.D.Cilett)