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Verilog_tigeress
- 我收藏的一些小技巧，适合刚开始学习verilog的朋友，养成好的编写习惯很重要哦~-collection of some small skills, suitable for the beginning of the study verilog friends, develop good habits is very important to prepare oh ~
compress VLSI结构设计研究
- 高速图像压缩编码器的VLSI结构设计研究.kdh 相当有水平的博士论文。里面详细讲到了如何设计小波变换VLSI结构。并对verilog hdl设计结构进行了评估
RK2728B_DATASHEET_brief_V0.3
- brief datasheet for RK2728 SoC
pll_verilog
- verilog model of a P-verilog model of a PLL
SDRAMController
- 璁茶Вsdram鐨勬搷浣滐紝闄勬湁verilog hdl浠ｇ爜
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
VLSI_Architectures_for_ECC
- This thesis devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density Parity- Check (LDPC) codes, and Reed-Solomon codes.-This thesis is devoted to sever
etd-0901103-165524
- jpeg 2000 modules with definate improved design ideas on the hardware platorm. especiallyy EBCOT and MQ coder.
SMCodingStyles
- verilog state machine coding style
FSMFundamentals
- Implementation of a Finite State Machine in Verilog !
Verilog+lab+3+-+HTN+lab+2
- a lab by vhdl, let discover and enjoy it now
verilogFPGA
- 介绍VERILOG语言的基础和应用，利用实例进行讲解-About the VERILOG language basic and applied, using examples to explain
8-channel-FIR
- b channel FIR filter verilog
高速图像压缩编码器的VLSI结构设计研究
- 高速图像压缩编码器的VLSI结构设计研究.kdh 相当有水平的博士论文。里面详细讲到了如何设计小波变换VLSI结构。并对verilog hdl设计结构进行了评估-The high-speed image compression VLSI architecture design of the encoder the study. Kdh quite the level of Ph.D. thesis. Which talked about in detail how to design VLSI
sabari
- My document includes basic examples in verilog coding
ahbTestbench_obf
- Verilog AHB Testbench
Verilog_A
- Verilog-A tutorial for circuit design
System-verilog-Overview
- Verilog overwied. it has writing verilog testbench guidlines
Verilog-HDL-Code-Examples
- various verilog code ezamples for brginners.good point to start with.
DLL-verilog
- verilog model of a D-verilog model of a DLL