搜索资源列表
verilog-hdl
- 王金明:《Verilog HDL 程序设计教程》,包括Verilog HDL的程序,对于初学者有一定的帮助-Wang Jinming: Verilog HDL programming tutorial, including Verilog HDL program, help for beginners
LED-verilog
- 利用verilog语言点亮led灯,基于2410开发板-The use of the verilog language lights led lights, based on the 2410 development board
16bit-Mulitiplier-Verilog-procedure
- 这是一个16位乘法器Verilog程序,包括有符号位和无符号位乘法器-This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier
21-bit--leading-adder-Verilog
- 这是一个21位超前进位加法器的verilog程序。-21 bit leading adder verilog program.
8-grade-4-pipeline-adder-Verilog
- 这是一个8位4级流水线的加法器的Verilog程序。-This is a eight grade 4 pipeline adder the Verilog program.
16-leading-adder-Verilog-program
- 这是一个16位超前进位加法器的Verilog程序。-This is a 16 bit leading adder verilog program.
verilog
- verilog 设计有关课件,是一个比较完整的verilog的ppt教程-verilog designing related resources
The Verilog golden Reference Guide
- 上传的目的很简单,就是赚积分,当然传的东西还要对得起大家,不然大家可是要吐口水的。 这是一个verilog的reference,英文版。因为要做一个verilog的解析器,所以就用到了这个。个人认为如果英语还可以(估计过4级就够了),想学verilog或是想找verilog参考的话,就直接看这本纯语法书,比其他那些垃圾东扯西扯卖弄技巧的强多了。 当然,这本书也提供了一些技巧,非常实用。强烈推荐,识货的快下!
Verilog-HDL
- 重点介绍verilog VHL语言结构及使用方法-Highlights verilog VHL language structure and use
fpga-verilog
- 基于fpga-verilog的音频设计,实现音频功能-the fpga-verilog Audio Design
Verilog-HDL
- verilog HDL程序入门,很好学,基本和C语言一样,几天就可以简单的编程-verilog HDL program entry, very good school, Basic and C language, a few days can be a simple programming
verilog
- 文档给出了verilog数字系统设计的6个实践项目的详细设计过程,包括设计思路、顶层设计和各个模块设计的源码和详细说明-The document gives 6 verilog digital system design practice project detailed design process, including source code and a detailed descr iption of the design ideas, the top-level design and m
pay-verilog
- 出租车计价器程序代码,硬件描述语言,VHDL—verilog-chuzuche meter,VHDL—verilog
wireareg--in-Verilog
- 辨析verilog编程中的wire与reg结构及用法-Discrimination verilog programming wire reg structure and usage
verilog
- 用verilog设计的存储器,可以读入数据,读出数据,是集成电路重要运用单元-Design with verilog memory that can be read into the data, read data is important IC with Cell
A-Verilog-Model-of-Universal-Sequence-Detector.ra
- a verilog model of universal seq detector
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码,实验资料,包括原理和代码,在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
verilog-uart
- UART(Universal Asynchronous Receiver Transmitter,通用异步收发器)是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路,分析UART的传输时序并利用Verilog HDL语言进行建模与仿真,最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive
Verilog-hardware-semantics
- Verilog硬件语义,深入了解Verilog语句和语义的编写。-Verilog hardware semantics and semantic understanding Verilog statement preparation.
Verilog
- verilog 语法结构概括总结,便于快速查找及快速入门-verilog syntax summarized, easy to quickly find and Quick Start