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FPGA-multiplier-on-chip
- 典型实例11.5 FPGA片上硬件乘法器的使用 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 本实例实现一个IIR滤波器，并在ISE里面进行仿真。 \rtl目录里面是源文件 \project目录里面是工程-Typical examples 11.5 FPGA chip hardware multiplier using the software development environment: ISE 7.1i hardware d
4-bit-Multiplier
- IT is a 4 bit multiplier vhdl coding file which is run in altera quatrs - II. in which 4 binary bit is multiplied and waveform can be obtained
wallacetree-16bit-multiplier
- 这是一种多功能的乘法器的设计思路,只要有了它,就能快速的解决乘法的问题,是卷积,求和,积分的好帮手.-This is a versatile multiplier design ideas, as long as you have it, you can quickly solve the problem of multiplication, convolution, summation, integral a good helper.
8bit-multiplier
- 8位二进制数乘法器VHDL实现8位二进制数乘法器设计，乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。 -8-bit binary multiplier VHDL 8-bit binary multiplier design, multiplication by itemized shift sum principle, starting from the least significant bit of
Chapter16-Multiplier
- 书籍《精通Verilog HDL语言编程》中第16章的程序实例代码，是关于常用乘法器的设计的，对于初学者有一定的帮助-Book "Proficient in Verilog HDL language programming" in Chapter 16 of the procedure code, the common multiplier designed for beginners will certainly help
multiplier-method
- 关于最优化算法的matlab仿真程序，乘子法。-Optimization algorithm matlab simulation program, the multiplier method.
serial-multiplier-using-generic-components
- Serial multiplier using generic components
dcm-multiplier-routines-
- dcm倍频例程及其用法。包含完整的dcm工程文件。具体代码内容请下载查看-dcm multiplier routines and their usage. Dcm file contains the complete works. Please see the specific code download
Vhdl-Implementation-of--Fast-32x32-Multiplier-Bas
- The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture base
module-multiplier
- 用vhdl编程，实现了一个2^N+1模乘法器，经验证，设计结果完全正确-use the vhdl language to design a module 2^n+1 multiplier
Multiplier-code-with-testbench
- VHDL code for synthesizable Multiplier with testbench
Structural-Pipeline-Multiplier
- Structural Pipeline Multiplier
booth-16_16-multiplier
- 由verilog编写的利用booth编码的16*16有符号乘法器的代码，没有pipeline-a 16*16 multiplier with booth coding by verilog
multiplier
- 乘法器的verilog工程文件，可以进行仿真实验，有详细解释，适合初学者学习参考。-Multiplier verilog project file, can be simulated, with detailed explanations, suitable for beginners to learn.
Multiplier
- 乘法器课程报告，华莱士树算法硬件实现，讲解详细-Multiplier course reports, Wallace tree algorithm implemented in hardware
Common-multiplier-design
- 常用乘法器设计，用FPGA能实现，值得下载。-Common multiplier design, FPGA can achieve, it is worth downloading.
GF-(q)-multiplier-design
- 伽罗华域GF（q）乘法器设计,FPGA实现-Galois field GF (q) multiplier design, FPGA realization
the-Lagrange-multiplier-method-
- 约束优化算法：拉格朗日乘子法matlab程序-Constrained optimization algorithm: the Lagrange multiplier method and matlab program
Verilog-code-for-multiplier
- VERILOG CODE FOR 16 BIT MULTIPLIER USING MODIFIED BOOTH ALGORITHM
floating-point-multiplier
- floating point multiplier in VHDL