搜索资源列表
Multiplier
- A multiplier unit in VHDL
multiplier
- this a multiplier in VHDL-this is a multiplier in VHDL
16bit_mult
- 16位的无符号数乘法器，自己写的，经得起验证，注释很详细-16-bit unsigned multiplier, its own written
dsa_code
- Verilog code for synthesis of 8-bit booth multiplier
doublemult
- 设计了一个双精度浮点乘法器。该器件采用改进的BOO TH 算法产生部分积, 用阵列和 树的混合结构实现对部分积的相加, 同时, 还采用了快速的四舍五入算法, 以提高乘法器的性能。把 设计的乘法器分为4 级流水线, 用FPGA 进行了仿真验证, 结果正确 并对FPGA 实现的时序结果 进行了分析。-Designed a double-precision floating-point multiplier. The device uses an improved algorithm fo
wallacetreemultiplier
- wallace tree multiplier n bit c program
wallace_tree_multiplier_part1
- wallace tree multiplier
GAFF
- 伽罗华域GF（q）乘法器设计,完整的源代码。-Galois field GF (q) multiplier design, the complete source code.
matrix3x3
- 3*3矩阵的乘法器代码!!! !!! !!! !!!!1-3* 3 matrix multiplier code~
multiplier8x8
- 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
ADSP-21262
- High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point
multiplier
- This file implemented a multiplier in VHDL
multiplier
- a multiplier in vhdl, contains an alu and a control unit
multiplier
- 个人收集的各种乘法器vhdl源代码，都经过验证，可以直接使用的。-Collected a lot of multiplier vhdl source code
CourseDesign
- 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
ade
- 用VERILOG HDL 语言实现一个8位串行乘法器-VERILOG HDL language with an 8-bit serial multiplier
mult_addtree
- 用VERILOG HDL 语言实现一个4位的流水线乘法器-VERILOG HDL language with a 4-bit pipelined multiplier
mutiplier_4bits
- 通过移位相加，实现两个数的相乘。通过一个内部寄存器存储得到的积。--- it multiplies a 5_bit multiplicand by a 5_bit multiplier to give -- an 8_bit product -- -- aim: to master the method of mutiplier "shift and add to realize the mutiplier" --
8by8multiplier
- Verilog HDL for 8*8 multiplier-Verilog HDL for 8*8 multiplier..