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code
- code for booths multiplier
freqm
- frequency multiplier
FinalFPMultiplier
- Simple 32 bit Floating point Multiplier
Boothsmul
- Booths Multiplier using Behavioral Model
DDS-baseddesignofthesinusoidalsignalgenerator
- 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度， 由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the singl
Multiplier
- 用VHDL语言仿真乘法器设计。能够实现一般乘法运算。-Multiplier using VHDL language design simulation. Multiplication can be achieved in general.
Multiplier
- 用VHDL语言描述的几个乘法器实例，如串行阵列乘法器等-VHDL language used to describe a few examples of multipliers, such as array multipliers, such as serial
multiplier_8_bit
- This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit)
WallaceTreeMultiplier
- Wallace Tree Multiplier in VHDL for 4bit operation fully using structural language
8bit_adder_AND_4x4_Multiplier
- 位加法器的verilog程序与4×4 乘法器的verilog描述-Verilog-bit adder of the procedures and 4 × 4 multiplier verilog descr iption! ! !
mul
- 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。 因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to
BoothMultiplier4
- Radix 4 Booth Multiplier
Galois_field_multiplier_verilog_design
- 伽罗华域GF（q）乘法器verilog设计.rar-Galois field GF (q) multiplier verilog design.rar
MUL
- 8-bit modified Booth s algorithm multiplier
16_bit
- 采用boot算法的16位乘法器,速度较快，可以试下哈-Boot algorithm using 16-bit multiplier, faster, you can try under the Kazakhstan
nxn_multiplier
- Verilog module for hardware N x N multiplier using generate keyword.
test_bench
- test bench for booth multiplier
Multiplier
- 4 bit multiplier written in behavioral VHDL, using logic gate logic. inputs are A and B (4 bit each) and output is C (8 bits).
FPGA
- 基于FPGA数字乘法器的设计：数字乘法嚣是目前数字信号处理中运用最广泛的执行部件之一，本文设计了三种基于FPGA 的数字乘法器．分别是移位相加乘法嚣、加法器树乘法器和移位相加一加法嚣树混合乘法器。通过对三种方案的仿真综合以厦速度和面积的比较指出了混合乘法器是其中最佳的设计方案-FPGA-based digital multiplier design: the number of multiplicative noise is the use of digital signal processin
BaughWooleyMultiplier
- Baugh Wooley Multiplier