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4-multiplier-_vhdl
- 4 bit multiplier which can be use for making projects......can also be stimulated on spartan kits
Multiplier-method
- 乘子法求解约束方程 老师编的一段程序 注释非常详细-Multiplier method to solve a series of constraint equations teachers very detailed program notes
MULTIPLIER
- 基于VHDL硬件描述语言设计的乘法器，位数可以修改-VHDL hardware descr iption language based on the design of the multiplier, the median can be modified
multiplier_ip
- 基于IP核的乘法器设计，multiplier_ip中包含完整的工程设计文件，用户可以在Xilinx ISE下运行-Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE
Multiplier
- VHDL语言设计的乘法器，经过试验箱测试通过，用试验箱的8个拨码开关输入数字，按键按下输出结果。-VHDL language design of multiplier, after chamber test, with the chamber of the 8 DIP switch input numbers, key press output.
lagrange-multiplier
- Larange Multipliers-Larange Multipliers...........
VHDL-based-8-bit-multiplier
- 基于VHDL的8位乘法器运算程序，运用移位迭代法运算得出-VHDL-based 8-bit multiplier operation procedures, the use of shift operations derived iterative method
multiplier
- 压缩的乘法器。是基于VERILOG 语言实现的，有较快的速度。-Compression of the multiplier. Is based on the VERILOG language, there is a faster speed.
carry-save-multiplier-Verilog-code
- 进位存储乘法器Verilog代码,该乘法器的显著特点是其性能取决于使用的硬件而与数据长度无关.-carry save multiplier Verilog code
lowpower-multiplier
- 32位无符号低功耗的乘法器,经过10000次测试,用smic.13工艺,DC综合后,延时为8ns,功耗仅为635uw.-it is an unsigned 32bit multiplier.100000 benchmarks have been tested and all of them passed. With smic 0.13um process library, after disign complier analysis, the clock period is 8ns,and th
8bit-Shift-and-Adder--multiplier
- 8位乘法器，经移位相加算法来实现的，用的VHDL语言-8-bit multiplier, adding the algorithm to realize the shift of
4-bit-multiplier
- 4 bit multiplier program using shift and multiply
mult
- 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete
Small-multiplier
- 小型倍频器，简单的介绍了如何用verilog写倍频电路》-Small multiplier
The-design-of-multiplier
- 国防科技大学的一篇高速乘法器算法的论文,应用于FPGA-National Defense University in a high-speed multiplier algorithm paper, used in FPGA
multiplier
- 几种verilog乘法器的代码，用于比较不同乘法器特点-Several multiplier verilog code, used to compare the different characteristics of the multiplier
booth
- radix 2 booth multiplier verilog code
VHDL-Multiplier
- 资料是EDA的一个课程设计，基于VHDL实现的乘法器，包含论文，欢迎下载-EDA data is a course designed to achieve a multiplier based on VHDL, including paper, please download
multiplier
- 参数可配置的sequential 乘法器和booth 乘法器-verilog source code with configurable parameters for sequential multiplier and booth multiplier
array-multiplier
- source code for array multiplier