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DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
TMS320DM642_SDRAM_PCB_Simulate
- TMS320DM642 SDRAM PCB预仿真-TMS320DM642 SDRAM PCB pre-simulation
Sun86
- SDRAM仿真文件，主要用于测试SDRAM的控制程序是否正确。-SDRAM simulation files, mainly used for testing control procedures SDRAM is correct.
blackfinL2_PDF_CHACHE_EBIU_SDRAM
- VISUAL DSP++ BLACKFIN DSP DESIGN CHACHE_EBIU SDRAM
newSD
- 基于Verilog的完整SDRAM控制器时序代码-Based on a complete Verilog timing SDRAM controller code
SDRAM_simulation_model
- sdram的测试程序 和读写程序 vhdl语言编写的-SDRAM testing procedures and to read and write procedures VHDL language
SDram_router
- 详细介绍sdram布线的方法，很实用的教程，摘自ee小站-Details SDRAM wiring methods, very useful tutorial, from ee station
sdram_hr_hw
- 在FPGA硬件上实现计算机通过串口发数据给FPGA，数据保存到SDRAM中，然后又返回给计算机串口。-In FPGA hardware realize computer data through the serial port issued to FPGA, the data saved to SDRAM, and then again back to the computer serial port.
ds_k4m511633c
- Datasheet for K4M511633C chip. It s a 8M x 16Bit x 4 Banks Mobile SDRAM from Samsung.
ddr2sdram_spartan3s700an.tar
- It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Sparta
modelsim_ddr2sdram_spartan3s700an.tar
- Modelsim DDR2 SDRAM files
testbench
- ddr sdram controller datd module source code
sdram_memdma
- blackfin开发板 BF533-sdram_memdma开发代码 包括sdram读写，dma使用 开发环境为visul dsp 3.5-development board Blackfin BF533-sdram_memdma development including SDRAM read and write code, dma use development environment for visul dsp 3.5
SDR_SDRAM_vhd
- SDR SDRAM的VHDL描述，比较详细，还有数据手册-SDR SDRAM the VHDL descr iption, more detailed, have data sheet
SDRAM
- C6000系列6713SDRAM的典型应用源程序 功能强大-C6000 Series Typical applications 6713SDRAM powerful source
sdramctrl2
- sdram controller in vhdl
IR_PEN
- infra pen controller, cmos sensor control and sdram control
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
DDRSDRAM
- DDR SDRAM的资料，有兴趣的朋友可以下下来-DDR SDRAM information, interested to see friends down under
SDRAMHDL
- SDRAM基础性控制核 很有用的 VHDL状态机实现-SDRAM control of the nuclear basic useful VHDL state machine implementation