搜索资源列表
Sdram_Control_4Port.Verilog写的sdram的控制器
- 已经验证可用。此代码为Verilog写的sdram的控制器，可以由用户的使用而加载到自己的项目中自行开发。,Have verified that is available. This Verilog code written sdram controller, can be loaded into the user' s use of their own self-developed projects.
Sdram_Control_4Port 用verilog写的sdram的控制
- 用verilog写的sdram的控制，进行sdram的读取和写入操作- sdram with the controllor based on verilog
sdram_vhdl_lattice.rar
- lattice sdram 控制器VHDL源代码,Sound code of Lattice Sdram Controller based on VHDL
EP3C25EVM.rar
- cyclone III EP3C25 开发板原理图,包括flash, sdram, usb, ethernet 等接口电路，可作设计参考。,cyclone III EP3C25 development board schematic diagram, including flash, sdram, usb, ethernet interface circuit, etc., can be used for design.
Micron_SDRAM_DDR2Simulation_mo
- DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme,DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
hssdrc_latest.tar.gz
- HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is li
SDRAM_VerilogCode.rar
- 基于FPGA的SDRAM控制器Verilog代码，开发环境为Quartus6.1，控制SDRAM实现对同一片地址先写后读。,FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.
HY57V641620HG.vp.rar
- Hynix公司8M Byte SDR SDRAM的Verilog语言仿真实现,Hynix' s 8M Byte SDR SDRAM Simulation of the Verilog language
DE2_70_D5M_LTM_NIOS_capture.zi
- 本文提供一個CMOS Controller，讓Nios II可以藉由CMOS Controller控制CMOS，並能讀出CMOS放在SDRAM中的影像。运行在DE2-70平台上,This article provides a CMOS Controller, so that Nios II can take advantage of CMOS Controller control CMOS, and allowed to deliver on the SDRAM in the CMOS imag
详细介绍了SDRAM的时序控制
- 详细介绍了SDRAM的时序控制，如果使用VHDL代码从SDRAM中读取数据。-Details of the SDRAM timing control, if you use VHDL code to read data from the SDRAM.
FPGA_DDR-SDRAM
- FPGA对SDRAM的控制，有部分源码，-FPGA SDRAM control, part of the source,...
source_code.rar
- 一些源程序，主要包括CAN总线驱动、sdram VHDL实现、ucos2的移植、SDIO驱动、tcpip的实现、usb控制器代码、基于FPGA的雷达目标模拟器等,Some source code, including CAN bus driver, sdram VHDL implementation, ucos2 transplant, SDIO drivers, tcpip of implementation, usb controller code, based on the FPGA, s
vga_core(vhdl).rar
- vga视频输出（vhdl），主要是从sdram中产生图形，输出到vga中,vga video outputs [vhdl], mainly arising from the SDRAM graphics, output to vga Medium
TEST.rar
- S3c2440硬件测试程序，主要功能包括：SDRAM读写测试，整片Falsh读写测试，Flash擦除，坏块检测，flash复制数据到SDRAM,S3c2440 hardware testing procedures, the main features include: SDRAM read and write tests, reading and writing test Falsh whole, Flash erase bad block detection, flash copy the
sdram 仿真模型
- sdram 仿真模型,用于verilog代码sdram行为级仿真-sdram modelsim model
sdram_ctrl1.rar
- FPGA读写SDRAM的VHDL程序，已经测试过,FPGA to read and write the VHDL procedures SDRAM have been tested
三星2410试验源码
- 三星2410试验源码,包括clock,nand ,sdram,led,key,timer,test-code of 2410,include clock,nand ,sdram,led,key,timer
SDRAM
- DSPC6747的SDRAM测试代码，分别向SDRAM中法写入数值，返回输入结果，验证写入成功。-DSPC6747 test code for SDRAM, SDRAM, respectively, China and France to write the value, return type results, verify the write success.
sdram_ver_134
- SDRAM控制器的源代码打包下载，不错不错值得-SDRAM controller source code pack download, well worth a good try
FPGA
- 结合FPGA和以太网传输的特点，设计了一套数据采集系统，应用FPGA的内部逻辑实现对ADC、SDRAM、网卡控制芯片DM9000的时序控制，以FPGA作为采集系统的核心，通过ADC，将采集到的数据存储到SDRAM中，以FIFO方式从SDRAM中读出数据，并将数据结果通过以太网接口传输到计算机-Combination of FPGA and Ethernet features, designed a data acquisition system, application FPGA' s i