搜索资源列表
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包,包括Verilog源代码,Doc说明文档,仿真DDR芯片模型,仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
fpga-dm9000a
- 一个项目工程,硬件包含XINLINX FPGA,配置FLASH,串口,SDRAM,与以太网芯片DM9000A,实现数据采集,以太网传输,电路验证完全正确,请放心使用,SPARTAN 3E 的BGA引脚320个,不容易布板,可以参考使用的。要FPGA实现网络通信也可以参考电路,B因为产品升级了所以公开原来的电路的。 -A project engineering, hardware contains XINLINX FPGA, configuration FLASH, serial port, SD
SDRAM_ipcore_
- Altera SDRAM ip核详解-Altera SDRAM ip nuclear Detailed
FPGA_SDRAM_PCI
- 一个基于FPGA的PCI数据采集程序,包括SDRAM控制,PCI9054时序控制,开发语言verilog,开发环境quartus-FPGA-based PCI data acquisition procedures, including SDRAM control, PCI9054 timing control, the development of language verilog, development environment quartusII
SDRAM
- verilog语言对SDRAM读写时序的描述,采用状态机结构实现的读写功能-timing of the SDRAM read and write verilog language descr iption, a state machine structure to achieve read and write capabilities
mem_ctrl_latest.tar
- 存储器控制FPGA程序,包括ram,fifo,sdram,flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
DDR_SDRAM
- ddr sdram 的控制程序,lattice的,比较好用的,大家-ddr sdram control program, lattice, and relatively easy to use, and we look
cameralink
- 由于目前基于CameraLink接口的各种相机都不能直接显示,因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统,该系统可以在不通过系统机的情况下,完成对相机CameraLink信号的接收、缓存、读取并显示 系统采用两片SDRAM作为帧缓存,将输入的CameraLink信号转换成帧频为75Hz,分辨率为1 024×768的XGA格式信号,并采用ADV7123JST芯片实现数模转换,将芯片输出的信号送到VGA接口,通过VGA显示器显示
AT91RM9200-AXD_SDRAM_DOWNLOAD
- 使用ATMEL AT91RM9200 CPU SDRAM初始化的一个例子。可以运行,初始化之后CS1的0x20000000地址可以访问。内部以文件的形式(Init_SDRam.txt)集成了ADS初始化命令配置,使得本工程可以直接下载到0x20000000地址运行,而不必限制于内部RAM。配置文件在AXD->Option->cfgInterface->session file中配置。祝好运,好使的话请给个推荐。上一个传错了,没改过的。这个对了。-ATMEL AT91RM9200
ts201_Test_SDRAM
- DSP TS201 Test SDRAM Over
sdram_test
- FPGA测试程序,使用XC3S250E对SDRAM进行读写的测试程序,SDRAM使用的是HY57V281620, 大小为128M。-FPGA test procedure, the use of XC3S250E SDRAM read and write on the test procedure, SDRAM using HY57V281620, size of 128M.
altera_sdram
- SDRAM控制器的VHDL代码在FGPA中的综合与实现-SDRAM controller VHDL code FGPA and implementation of integrated
ddr_ddr2_sdram9.0
- altera 公司提供的ddr_ddr2_sdram9.0,DDR2 SDRAM 源代码-altera provided ddr_ddr2_sdram9.0, DDR2 SDRAM source code
fpga
- fpga+sdram+PHY 芯片设计原理图-fpga+ sdram+ PHY chip design schematic
verilog_sdram
- SDRAM读写控制的实现与Modelsim仿真,采用verilog HDL编写-sdram controller and simulate with modelsim
altera_sdram
- Simple SDRAM controller source code for Altera DE2 board
Sdram_Control_4Port
- SDRAM控制器HDL实现,sdram为美光公司的-sdram controller
Sdram_Control_4Port
- DE2开发板提供的四端口SDRAM驱动,用户不需要对SDRAM直接操作,把SDRAM对用户透明化-DE2 development board provides four-port SDRAM drive, users do not need to direct the operation of the SDRAM, the SDRAM transparent to users
sdram_design
- SDRAM存取控制器设计书,包含标准的SDRAM读写控制功能,和自动刷新功能。对VHDL设计初学者很有帮助。密码MMCTEAM。-SDRAM access controller design books, contain standard SDRAM read and write control functions, and auto refresh function. VHDL design helpful for beginners. Password MMCTEAM.
micron_sdram_simulation_model
- micron各种规格的SDRAM的仿真模型及详细设计资料,基于verilog语言。-micron variety of SDRAM simulation model and detailed design information, based on the verilog language.