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systemverilog
- systemverilog是新出现的一种高级硬件描述和验证语言，这里给出了一些书和文章还有使用vmm方法开发testbench的例子
SystemVerilog
- Systemverilog 的中文资料 比较简单
systemverilog
- systemverilog简介如果能给大家一点帮助的话我会感到很高兴的
amba3core.rar
- amba3 sva 完全验证的代码，有verilog的和systemverilog的,amba3 sva fully validate the code, and the Verilog and SystemVerilog
hssdrc_latest.tar.gz
- HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is li
SATA_Verification_IP-SystemVerilog
- SATA Verification IP - SystemVerilog,是使用FPGA做的sata接口部分，是一篇文档-SATA Verification IP- SystemVerilog, is to use FPGA to do sata interface part, is a document
SystemverilogSource
- systemverilog程序，需要的朋友可以参看-SystemVerilog procedures need friends can see
SystemVerilogAssertions
- Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions
SystemVerilog
- 非常好的SystemVeriog资料和代码。-SystemVeriog very good information and code.
systemverilog
- system verilog 是国际流行的设计和验证语言，根据语言的特点分为两部分:for设计和for验证。另外一种书是介绍如何应用system verilog, 如果你要用syntem verilog, 推荐先读一下。-system verilog is popular hardware design and verification language. The languange compose of two part: systemverilog for desin , system ve
SystemVerilog
- SystemVerilog语言在数字系统设计及验证中的应用-SystemVerilog language in digital system design and verification of
systemverilog
- a good book on system verilog
SystemVerilog_For_Design_Springer_2nd_Ed_2006
- SystemVerilog For Design (Springer-2nd_Ed-2006)-SystemVerilog For Design (Springer-2nd_Ed-2006)
SystemVerilog
- 很好的SystemVerilog例子- very good
SystemVerilog
- 关于SYSTEMVERILOG的语法，一些例子-About SYSTEMVERILOG syntax, examples and so on. . . . . . .
SystemVerilog
- SystemVerilog 是一个硬件测试语言。可以搭建测试平台。本书有很多的测试用例。并且会告知你如何使用该语言。-SystemVerilog for Verification A Guide to Learning the Testbench Language Features Second Edition
SystemVerilog-Testbench-Constructs
- 用SystemVerilog编写testbench-SystemVerilog Testbench Constructs
Systemverilog Constraint examples
- Systemverilog constraint random verification examples
[IEEE]SystemVerilog.std.1800-2012.pdf
- [IEEE]SystemVerilog.std.1800-2012
SystemVerilog IEEE Std 1800-2012
- SystemVerilog IEEE Std 1800-2012