搜索资源列表
SFIFO_8960
- 异步FIFO设计，简单适用，非常好用，节省资源。-Applicable asynchronous FIFO
FIFO_V1
- 同步FIFO和异步FIFO程序，希望对大家有用！verilog程序。-Synchronous FIFO and asynchronous FIFO procedures, and hope to be useful! The verilog procedure.
fifoVerilog
- 设计一个异步FIFO，完成数据平滑功能，FIFO的深度为256，宽度为8位，实时给出读空和溢出指示，写时钟为带间隔的100MHz，读时钟为5MHz，代码为了便于读阅，存放在word文档，可直接拷贝到quartus或者ise编译平台下使用-Design an asynchronous FIFO, complete data smoothing function, the depth of the FIFO 256, and the width is 8 bits, real read empty
asy_fifo
- 异步FIFO的实现方法，配源程序和WORD说明-Asynchronous FIFO implementations with source code and WORD Descr iption
asyn_fifo_bk
- 该verilog代码位手动编写的异步fifo。-This code is manually generated asychronous fifo.
FIFOverilog
- 异步FIFO实现数据先入先出的存储方式基于verilog HDL语言-Asynchronous FIFO first-in, first-out data storage based on Verilog HDL language
sync-and-asyn_FIFO_verilog
- 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
fifo12_12
- 异步fifo.能够实现异步缓冲数据，希望大家能够有帮助-Synchronous fifo, to achieve synchronization of the buffer, the hope that useful
Chapter-9
- 9.1 异步FIFO设计实例 9.2 DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
101906
- 异步fifo的资料整理 帮助学习fifo的设计-some docs about asyn fifo
async_fifo-and-verilog
- 异步fifo的详细原理分析说明及verilog源代码，经典推荐！-Detailed descr iption of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
syn_fifo
- 关于FPGA同步FIFO和异步FIFO的编写和设计方案-Writing and design on FPGA synchronous and asynchronous FIFO FIFO
fifo2
- 异步fifo 先进先出 用于缓冲数据，用verilog HDL所写，在quartus II中测试通过，modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
FIFO.v
- 异步先进先出FIFO存储器，采用格雷码判定，消耗资源更小-Asynchronous FIFO FIFO memory, using Gray code determination, consume less resources
FIFO
- fifo异步串口收发程序 FPGA程序-fifo asynchronous serial transceiver
Asynchronous_FIFO
- 异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modifications.
syn_fifo_style_1
- verilog实现的，异步FIFO。所有代码在一个模块中。-verilog achieve, asynchronous FIFO. All code in a module.
syn_fifo_style_2
- 由verilog实现的，异步FIFO，分为多模块实现。-Verilog achieved by the asynchronous FIFO, divided into multiple modules.
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
fifo
- 先入先出FIFO，实现缓存功能，异步的还实现转换频率的功能，在FPGA里十分常用。-FIFO,First input,First output