搜索资源列表
DPLL
- 数字锁相环DPLL实例程序，帮助理解PLL的结构和详细原理-DPLL DPLL examples of procedures to help understand the structure and PLL detailed Principle
dpll_4
- 实现4阶数字锁相环，老外写的，有详细注释，如果您觉得不错，就re一下-achieve four bands DPLL, a foreigner writing a detailed notes, if you think it's good, what re
2005117163755
- MPSK解调的关键在于载波同步和码元同步．这里采用 数字锁相环实现载波同步和码元同步。-MPSK demodulator is the key carrier synchronization and code synchronization. Here digital PLL carrier synchronization and code synchronization.
verilogpll
- 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
PLLprogram
- 数字锁相环程序，适合于FM、AM开发 数字锁相环程序，适合于FM、AM开发-DPLL procedures for FM, AM Development DPLL procedures for FM, AM Development
PLLpro
- 关于数字锁相环的使用，结合FM,AM的使用来说明-DPLL on the use of combined FM and AM to illustrate the use of
010919.pdf
- 全数字锁相环ＶＨＤＬ描述并实现功能仿真，另附有图形说明-DPLL VHDL descr iption and achieve functional simulation, followed by graphic shows
DDScom
- 直接式数字锁相环频率合成器.用ELANIX公司SYSTEMVIEW运行.-direct digital PLL frequency synthesizer. SYSTEMVIEW ELANIX companies with operations.
pll_improvement
- 一种改进的全数字锁相环设计 一种改进的全数字锁相环设计-an improved DPLL design an improved design DPLL
VHDLDPLL
- 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
数字Costas环的设计与实现
- 针对扩频系统的载波同步, 研究了数字Costas 环的设计和实现方法。介绍了数字Costas 环的结构、实现载波同步的基本方法。以二阶环为例, 分析了数字锁相环的环路滤波器的参数设计方法, 为数字Costas 环的设计提供了参考。提出了在高速信号处理板(以FPGA 和DSP 为基础) 中数字Costas 环的实现方案, 经工程验证, 能够实现载波同步, 解调出所需信号.
dxz
- 低相噪、低杂波数字锁相环路滤波器的设计,caj格式，下载前请安装相应阅读器-Low phase noise, low-noise digital phase-locked loop filter design, caj format, download the pre-install the corresponding reader
006
- 基于FPGA实现的一种新型数字锁相环-Based on the FPGA realization of a new digital PLL
newDPLLdesign
- 使用VHDL语言进行数字锁相环的设计，pdf格式，可以打开-The use of VHDL language design of digital phase-locked loop, pdf format, you can open
pll
- 实现同步时采用锁相环，锁相环实现的原理，及源代码，-Implementation of the principle of phase-locked loop, and the source code,
shuzisuoxiang
- 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of
PLL
- 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation
84f704a6df6c
- 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。-MC145159 PLL frequency synthesizer design and realization of PLL frequency synthesizer the basic principles of integrated PLL chip M C 145159 work characteristic
dpll
- 数字全锁相环的介绍文章，讲述了数字锁相环的实现原理和实现步骤(The introduction of the digital full phase locked loop is introduced, and the realization principle and the implementation steps of the digital phase locked loop are described)
基于DSP28335的单相PWM整流 双闭环PI控制
- 利用DSPF28335实现单相桥式PWM整流器的双闭环PI控制，用到AD7606和数字锁相(Double-closed-loop PI control of single-phase bridge PWM rectifier using DSPF28335, using AD7606 and digital phase lock)