搜索资源列表
C51锁相环
- 基于C51的锁相环，可修改锁相环所存时间(Phase locked loop based on C51)
锁相环PLL算法
- 该算法是介绍三相软件锁相环源代码，通过C编写(PLL algorithm source code)
Epwm_start
- 采用锁相环控制电机转速，能达到万分之几的精度(The motor speed is controlled by a phase-locked loop.)
one_phause_pll
- 描述： 单相锁相环仿真模型，适用于想了解PLL的同学。(a Phase Lock Loop (PLL) closed-loop control system, which tracks the frequency and phase of a sinusoidal signal by using an internal frequency oscillator. The control system adjusts the internal oscillator frequency to ke
PLL0324
- 风力发电并网matlab方针锁相环控制源码(feng li fa dian PLL matlab)
xianggan
- 使用costas锁相环实现载波同步提取相干载波，可以自由设定初始数据(Using Costas phase locked loop to realize carrier synchronization extraction of coherent carrier, the initial data can be set freely.)
zip
- 基于序阻抗的直驱风电场次同步振荡分析与锁相环参数优化设计((impedance modeling +PLL modeling) sequence impedance of direct drive wind power farm subsynchronous oscillation analysis and parameter optimization design based on PLL)
PLL
- verilog编写的锁相环程序。可以对照参考(Verilog prepared by the phase-locked loop program. Can control reference)
dpll
- 数字全锁相环的介绍文章，讲述了数字锁相环的实现原理和实现步骤(The introduction of the digital full phase locked loop is introduced, and the realization principle and the implementation steps of the digital phase locked loop are described)
PLL
- 一个基于二阶广义积分器的锁相环仿真模型，可以测得三相正弦信号的相位和频率(Phase-locked loop simulation model based on Nikai Hiroyoshi integrator)
dpll源程序
- 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the pha
锁相环频率合成
- 基于51单片机的锁相环频率合成器的设计。使用PLL集成芯片CD4046，可编程分频芯片CD4522（同MC14522），使用LCD1602显示，频率由按键输入。标准输入信号为1khz方波。(Design of PLL Frequency Synthesizer Based on 51 single chip microcomputer. Using PLL integrated chip CD4046, programmable frequency division chip CD4522 (M
BDStracking
- 究采用锁频环和锁相环相结合的方法来实现载波跟踪(The configuration of carrier tracking, which combining FLL with PLL.)
PLLsuoxianghuan
- PLL锁相环的仿真，自己搭建的模型，可以有效实现相位的跟踪。(PLL simulation, build its own model, can effectively achieve phase tracking.)
a3 - 副本
- 广义积分器锁相环仿真 中间很多问题 还不会改 以后有空再改(There are many problems in the simulation of the generalized integrator phase lock loop simulation.)
TwoOderPll
- 1、资料包含二阶环路设计简要说明，Matlab程序，Matlab程序模拟FPGA工作方式，对各变量进行了量化处理 2、资料包含使用Vivado2015.4.2版本的工程文件，可直接运行查看仿真结果 3、参考资料为杜勇老师的《锁相环技术原理及其FPGA实现》(1. The data include a brief descr iption of the second-order loop design. The MATLAB program and the MATLAB program sim
pll
- 自己用matlab编写的平方锁相环的仿真，对锁相环研究的同学具有很好的参考价值(The simulation of PLL written by myself in MATLAB is of great reference value to the students who study PLL.)
锁相环的matlab环路仿真
- 该模型可以用于计算二阶三阶和四阶锁相环的环路参数，并且能够根据环路参数进行环路稳定性和带宽的仿真。
锁相环输入信号建模例程
- 锁相环输入信号建模例程，代码注释详细，例如初学者，将输入信号转换成8bit补码数据写入txt文件，可用于FPGA工程测试使用。还可以直接绘出时域波形图，直观比较。
MINI_INV_v1
- 自己毕设用的单相并网逆变器程序，使用的是TI公司的DSP28335，包括了锁相环PLL，PR控制等子程序(The program of single-phase grid-connected inverters is designed by ourselves. It uses TI's DSP28335, including PLL, PR control and other subroutines.)