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div_32bits
- 以ISE为平台，VHDL语言编写的32位补码整数除法器模块，只需在Top模块中调用即可-As a platform to ISE, VHDL language complement 32-bit integer division module, simply call the module to Top
verilog
- 這是一個除法器演算法，是利用移位的方式進行除法運算-This is a divider algorithm is the use of division shift the way
12
- 4位除法器 library IEEE use IEEE.std_logic_1164.all use IEEE.std_logic_unsigned.all entity fpdiv is port ( DIVz: out STD_LOGIC A: in STD_LOGIC_VECTOR (3 downto 0) B: in STD_LOGIC_VECTOR (3 downto 0) data_out: out STD_LO
dcf089f8-85a5-44b9-98d9-e667ba564784
- 除法器能够做除法运算能够做除法运算 除法器能够做除法运算能够做除法运算-Divider can do can do division division
div
- 四位除以四位除法器，VHDL语言描述，quaruts工程-Four divided by four divider, VHDL language descr iption, quaruts Engineering
Fixpoint-Divider
- 定点除法器的设计,关于定点除法器的原理，和设计，以及电路设计-Fixpoint Divider Design
DIVIDA
- 20位除法器，vhdl语言所写的，不错的代码，仅供参考-20 divider, vhdl language written
zuhe
- 这个是12位的除法器，进过验证的，verilog程序，应用组合逻辑，欢迎下载-This is 12-bit divider, been to verification, verilog, application logic combinations are welcome to download
divider
- 16位定点无符号数除法器，除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成-Unsigned 16-bit fixed-point divider, divisor, dividend by 16-bit integer and 16 fractional bits, commercial 32-bit integer and 16 by the decimal form, the remainder from 32 fractional bits
verilog_Common_arithmetic
- 常用逻辑运算，加法器，乘法器及除法器的verilog语言，可用modelsim或Quartus II 9.0环境-Common logic operation, adder, multiplier and divider verilog language, can be used modelsim or Quartus II 9.0 environment
VHDLchufaqi
- 针对8位的数据进行除法器的设计及实现，最后经编译通过。-Data for the 8-bit divider design and implementation, and finally by the compiler.
diivider4
- 四位除法器，写的算法布扎带，想下就下，不下也行-Four divider, with a written calculation Fabu Zha, think the next on the next, no less will do
chengxu
- 4位乘法器，4位除法器，K倍频的VHDL实现-Four multipliers, four dividers, K multiplier of VHDL
VHDL-test-code-divider
- VHDL实验代码：除法器，是一个基于VHDL语言开发的小程序，是关于除法的算法，比较实用-VHDL test code: divider, is a VHDL-based language developed by a small program, on the division algorithm, more practical
chufa
- 描述一个4位除法器，实现，包含源代码，及其其它说明-Describe a 4-bit divider, and includes source code, and other instructions
chufaqi
- EDA课程设计，实现带符号五位除法器，包含所有源代码及课设报告。-EDA program design, implementation, signed five divider, includes all source code and class design report.
combinational_divider
- 参数可配置的除法器verilog源代码，验证通过-verilog soure code for divider with configurable parameters
div
- 32位整数阵列除法器，verilog代码编写，性能高效。-32-bit integer array divider, verilog coding, performance and efficient.
shenfaqi
- 設計一個除法器電路，輸入 8 -位元的被除數 A 與除數 B ，輸出為商 Q=A/B及餘數R。-Design a divider circuit, type 8- bit of the dividend A and divisor B, output of business Q = A/B and the remainder R.
Frequency-counter
- 基于FPGA的数字频率计：1. 测量1Hz～1GHz方波的频率，精度为十分位。 2. 档位自动调整，分为1Hz~999.9Hz,1KHz~999.9KHz,1MHz~999.9MHz三个档位。 3. 实现16位的除法器，进行频率的计算，并以ASIIC码输出测量的数据。 -FPGA-based digital frequency meter: 1. Measurement 1Hz ~ 1GHz square wave frequency, accuracy decile. (2)