搜索资源列表
divider
- 除法器,经过验证,性能优良,值得下载,应该是定点除法的-divider,it is verified and good performance
74845002vhd_divider
- 除法器,用于求余用算,流水线性运算,, -Divider, for the remainder used to count
divider
- verilog的除法器 有多重方法 很适合初级者阅读-verilog divider multiple method is very suitable for beginners to read
实例模块
- 各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench
divider
- 用verilog实现一个被除数位8位、除数为4位的高效除法器-Verilog to achieve a dividend of 8, division by four efficient divider
chufa
- 用VHDL设计的四位除法器,可以实现四位二进制数的除法操作-Four divider with VHDL design, you can achieve the four binary division operation
divider
- 基于移位相减运算的除法器设计,完整的设计工程文件在divider文件夹下-Based on the shift subtraction divider design, complete design project file divider file folder
VHDL_book2
- add4a:4位加法器的设计 add8a:8位加法器的设计 subtract:4位减法器的设计 addsub: 4位加法器/减法器的设计 shift4:移位寄存器的设计 mult4:乘法器设计 div8:除法器设计 alu4:算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtraction Design addsub: 4-bit ad
div16d8
- 16位除以8位除法器,Verilog HDL语言-16 divided by 8 divider, Verilog HDL language
BCD_ALU
- bcd码的ALU单元,包含全加、全减、乘法、除法器-bcd code ALU unit, including All-Canadian, all subtraction, multiplication, division, unit
seq_div
- 除法器设计 样例程序-Divider design sample program
divider_with_cache
- 带缓存的除法器,包括test bench,在普通除法器上加上缓存功能-divider with cache
div_nonrestoring
- 用verilog 实现的除法器 ,被除数32位 除数为16位-Divider using verilog realize the dividend 32 divisor is 16
BCD_divid_new
- VHDL语言编写的8位BCD除法器,可以实现浮点数计算,只支持正数运算,并用isim进行仿真-VHDL language 8 BCD division, can achieve floating-point calculations, which only supports a positive number arithmetic, and use isim simulation
divider_VERILOG
- 采用VERILOG实现硬件除法器。提供RTL代码和仿真文件。-Achieved using VERILOG hardware divider. Provide RTL code and simulation files.
SUANSHUJISUAN
- 通过verilog hdl实现加法器乘法器,除法器的设计-Achieved through verilog hdl adder multiplier, divider design
a
- 用verilog实现除法器,调用了ip核,不仅有源代码,还有测试程序的时序编写-verilog ise divider
lab4_5
- 用VHDL实现串行除法器,16位被除数,8位除数-Using VHDL serial divider, 16 dividend, divisor 8
divider
- 位数可以任意修改的除法器,本人亲自测试,可以使用,效率和使用资源都是很少的-its a very good divider based on Verilog HDL
div
- 这是我用verilog写的一个电平触发的一个除法器,文件在压缩包内,开发环境是Quartus II。-this is a file of divide using verilog language.