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chufaqi
- 介绍了一种使用可编程逻辑器件FPGA和VHDL语言实现32位除法器的设计方法。该除法器不仅可以实现有符号数运算,也可以实现无符号数的运算。-A programmable logic device FPGA and VHDL design of the 32 divider. The divider can be achieved not only symbolic arithmetic, unsigned op.
streamline_divider
- streamline 除法器，是国外一个工程师所写,verilog语言，modelsim测试-streamline divider
chufaqi
- 64位除法器，可计算商和余数，时序，测试通过-64bit divider
divider
- 里面的是关于一个阵列除法器的代码，很详细。-It is about a array except of religious code, very detailed
atmel-asm
- 16位除法器，以及16进制数转10进制数 使用ATMEL的汇编语言编写-16bit Divider,Only for Atmel Development environment
chufaqi
- 电子学课程设计--有符号5位整数除法器设计与制作-Signed5 bit integer divider design and production
divider
- 基于FPGa的32为除法器，从别的地方搞来的，给大家共享以下，算是做贡献。-Divider based on the FPGA 32, to engage in from somewhere else, to share the following to be considered to contribute to.
ISE-graphics
- 3D图形，单精度浮点乘法器，单精度浮点除法器，单精度浮点乘累加器-3D graphics,single float pointing multiplier, single float pointing divider,single float pointing MAC
divider
- 除法器设计，有详细的步骤-Design of divider, detailed steps
immediate_float_divide_module
- 单精度浮点数除法器。用组合逻辑实现。高精度。-Single-precision floating point divider.
Divider
- 一个除法器的FPGA代码设计 Divider-fpga Divider
divider
- verilog很省资源的除法器，（用减法，需要时钟）验证通过-Province resources division, verified by
divider
- VERILOG编写的24位除法器代码核，是FPGA或者ASIC设计中的一核心计算模块。-VERILOG written 24 divider code nuclear FPGA or ASIC design in a core module.
Div
- 非常好用的小数除法器，verilog开发的。quartusii下综合通过-Very easy to use fractional divider, verilog developed. quartusii under comprehensive by
verilog_example
- verilog实例，多路器，除法器，数字跑表的多种实现方法-verilog example, the multiplexer, a divider, a digital stopwatch many implementations
VHDL-divider
- 8位数除法器，用的软件是quartus，被除数是8位的，除数4位-8-digit division, software quartus dividend is 8, the divisor 4
FPGA_Divider
- FPGA实现除法器的功能，并行逻辑计算，输出结果为商和余数。适用于FPGA内部无IP核等的低端FPGA器件上。-Function of Divider based on FPGA logic,output result includes the quotient and remainder. This function is applied to the low-end FPGA devices
COP2000-experimental-instrument
- 计算机组成原理 利用COP2000实验仪自行设计指令系统实现乘法器和除法器实验指导-Principles of Computer Organization the use of COP2000 experimental instrument design their own instruction set multiplier and divider experimental guidance
Verilog_divid
- vhdl语言描述传统除法器，传统乘法器的改进，从原理到实现的传统除法器-vhdl language to describe the traditional divider, the improvement of traditional multiplier principle to achieve the traditional divider
div1
- Verilog HDL语言16位除法器，已通过测试-Verilog HDL 16 division