资源列表
main_seral
- 《MATLAB神经网络原理与实例精解》，第六章中的例子——串行方式训练BP网络（实现性别识别）-" MATLAB network principles and examples of fine solution nerves," Chapter VI examples- serial BP network training (to achieve gender identification)
main_xor
- 《MATLAB神经网络原理与实例精解》，第六章中的例子——BP网络实现异或逻辑-" MATLAB network principles and examples of fine solution nerves," Chapter VI examples BP network XOR logic
Greed-Snake
- 电脑桌面上的小游戏贪吃蛇，java语言编写，结构清楚，适合初学者。-Game Snake on your desktop, java language, structure clear, suitable for beginners.
diagnose
- 《MATLAB神经网络原理与实例精解》中chap13中的例子 基于概率神经网络的柴油机故障诊断-Diesel Engine Fault Diagnosis based probabilistic neural network- " MATLAB network principles and examples of fine nerve Solutions" in chap13 examples
java-gobang
- 使用java语言编写的电脑桌面小游戏五子棋，包括MainFrame和MainPanel两个类，适合java初学者学习。-Use java language of small desktop computer games backgammon, including MainFrame and MainPanel two classes, suitable for beginners to learn java.
calculator
- 使用java语言编写的计算器，具有常用计算器所使用的功能，适合java语言初学者的学习。-Using java language calculator, calculator with a common-use features for beginners to learn java language.
Elman-network-prediction-
- 《MATLAB神经网络原理与实例精解》中chap13的例子 Elman网络预测上证股市开盘价-" MATLAB network principles and examples of fine nerve Solutions" in the example of Elman network prediction chap13 Shanghai stock market opening
BP
- 《MATLAB神经网络原理与实例精解》中chap13的例子 基于BP网络的个人信贷信用评估-" MATLAB network principles and examples of fine nerve Solutions" in the example chap13- Based on BP Network personal credit credit assessment
gL
- 《MATLAB神经网络原理与实例精解》中chap13的例子 基于概率神经网络的手写体数字识别-" MATLAB network principles and examples of fine nerve Solutions" in the example chap13- Based Probabilistic Neural Network handwritten numeral recognition
use-GUI
- 《MATLAB神经网络原理与实例精解》中chap11的例子 用GUI设计神经网络-Examples of " MATLAB network principles and examples of fine nerve Solutions" in chap11- A neural network with GUI design
led_display
- Verilog HDL 点亮LED灯，程序简单，适合新手练习上手，简单易懂。-Verilog HDL lit LED lights, simple procedures, suitable for beginners to practice to use, easy to understand.
dds_clk
- FPGA工作时钟位50MHz，通过引出FPGA时钟信号，供给外部DDS模块使用。-FPGA clock work bit 50MHz, led by FPGA clock signal supplied to the external DDS module.