资源列表
random_num_gen
- 通过随机数产生原理进行verilog编程，从而实现FPGA的随机数产生(Through random number generation principle for Verilog programming, so as to achieve the FPGA random number generation)
PLL
- 通过对输入时钟进行锁相环IP核配置，产生所需的时钟信号(By configuring the input clock PLL, the IP core generates the desired clock signal)
串口V3
- 用VC++MFC开发的上位机的串口通讯，发送并接收下位机数据(Serial communication of upper computer)
调制识别
- 提供了一个调制信号发射程序，以及误码率分析程序，(Provides a modulation signal emission procedures, and bit error rate analysis procedures,)
wlan1
- math lab code, wireless net, csma ca
ideal_pll
- 本程序仿真了常用的理想二阶环路，对于研究锁相环大有裨益。(This program simulates the commonly used ideal two order loop, useful for the study of phase-locked loop.)
RC_PLL
- 本程序用matlab m文件仿真rc二阶环，对于通信领域研究人员来说，同步问题非常重要，工程常用二阶环对于初学者大有裨益。(This procedure uses Matlab m file simulation RC two level ring, for the field of communication researchers, synchronization is very important, the project commonly used two steps ring for
msxml61011_33lc.com
- qt做的电子相册，能够添加本地图片并且播放，实现了图片左右旋转和放大缩小等等(Qt do electronic albums, can add the local pictures and play, realize the picture the left-right rotating and zoom-in and so on)
ARQ
- ARQ通信过程仿真，附带GUI图；已经编译通过。(communication process simulation)
实验0-1 Template工程模板-新建工程章节使用
- 实验0-1 Template工程模板-新建工程章节使用(Experiment 0-1 Template engineering templates - new engineering chapter use)
CRC16校验工具
- crc16 modbus CRC16校验工具C#源代码，开发环境C#，源代码开源免费(CRC16 check tool c # source code, development environment c #, source open source free)
故障仿真
- 根据书上的说明仿真了冲击故障，转子失衡故障，及转子碰磨故障(According to the instructions of the book, the impact failure, rotor imbalance fault and rotor collision fault are simulated)