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文件名称:verilogsourcecode

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [WORD]
  • 上传时间：
    2012-11-16
  • 文件大小：
    3.42mb
  • 已下载：
    0次
  • 提 供 者：
    徐****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

提供了verlog完整工程文件、设计源文件和说明文件-Provides a verlog complete project file, design source files and documentation
(系统自动生成,下载前可以参看下载内容)

下载文件列表

verilogsourcecode/Example-b8-6/des.doc
verilogsourcecode/Example-b8-6/Synplify_Pro/ALU_Syn_2.prd
verilogsourcecode/Example-b8-6/Synplify_Pro/ALU_Syn_2.prj
verilogsourcecode/Example-b8-6/Synplify_Pro/ALU_Syn_demo.prd
verilogsourcecode/Example-b8-6/Synplify_Pro/ALU_Syn_demo.prj
verilogsourcecode/Example-b8-6/Synplify_Pro/ALU_Syn_demo.sdc
verilogsourcecode/Example-b8-6/Synplify_Pro/Mix_src.prd
verilogsourcecode/Example-b8-6/Synplify_Pro/Mix_src_vhdl.prd
verilogsourcecode/Example-b8-6/Synplify_Pro/Mix_src_vhdl.prj
verilogsourcecode/Example-b8-6/Synplify_Pro/Mix_src_vlog.prd
verilogsourcecode/Example-b8-6/Synplify_Pro/Mix_src_vlog.prj
verilogsourcecode/Example-b8-6/Synplify_Pro/MyWorkspace.prd
verilogsourcecode/Example-b8-6/Synplify_Pro/MyWorkspace.prj
verilogsourcecode/Example-b8-6/Synplify_Pro/source/VHDL/ALU.VHD
verilogsourcecode/Example-b8-6/Synplify_Pro/source/VHDL/HDL_DEMO.VHD
verilogsourcecode/Example-b8-6/Synplify_Pro/source/verilog/ALU.V
verilogsourcecode/Example-b8-6/Synplify_Pro/source/verilog/HDL_DEMO.V
verilogsourcecode/Example-b8-6/Synplify_Pro/source/mixed/vhdl/mux.v
verilogsourcecode/Example-b8-6/Synplify_Pro/source/mixed/vhdl/mux21.vhd
verilogsourcecode/Example-b8-6/Synplify_Pro/source/mixed/vhdl/reg8.v
verilogsourcecode/Example-b8-6/Synplify_Pro/source/mixed/vhdl/rotate.v
verilogsourcecode/Example-b8-6/Synplify_Pro/source/mixed/vhdl/top.vhd
verilogsourcecode/Example-b8-6/Synplify_Pro/source/mixed/verilog/mux.vhd
verilogsourcecode/Example-b8-6/Synplify_Pro/source/mixed/verilog/mux21.v
verilogsourcecode/Example-b8-6/Synplify_Pro/source/mixed/verilog/reg8.vhd
verilogsourcecode/Example-b8-6/Synplify_Pro/source/mixed/verilog/rotate.vhd
verilogsourcecode/Example-b8-6/Synplify_Pro/source/mixed/verilog/top.v
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/.recordref
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/layer0.tlg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/layer1.tlg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/layer2.tlg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/stderr.log
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/stdout.log
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1.fse
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1.srd
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1.srm
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1.srr
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1.srs
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1.sxr
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1.tcl
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1.vqm
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1.xrf
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1_cons.tcl
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/top1_rm.tcl
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/syntmp/mux.plg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/syntmp/rotate.plg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/syntmp/top.plg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_3/syntmp/top1.plg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/.recordref
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/AutoConstraint_top.sdc
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/layer0.tlg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/layer1.tlg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/layer2.tlg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/stderr.log
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/stdout.log
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top.fse
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top.srd
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top.srm
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top.srr
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top.srs
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top.sxr
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top.tcl
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top.vqm
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top.xrf
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top_cons.tcl
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/top_rm.tcl
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_2/syntmp/top.plg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU.fse
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU.srd
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU.srm
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU.srr
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU.srs
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU.sxr
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU.tcl
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU.tlg
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU.vqm
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU.xrf
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU_cons.tcl
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/ALU_rm.tcl
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/AutoConstraint_alu.sdc
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/fsmviewer.fsm
verilogsourcecode/Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.fse
verilogsourcecode/Example-b8-6/Synpl

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