资源列表
fir
- 先用matlab得到所需滤波器的系数，将AD采样的数据经过fir滤波器后输出-First to use matlab to obtain the required filter coefficients, data from the AD sample, after the output filter through the fir
lab4
- vhdl uart lab ENTITY uart IS PORT ( SIGNAL clock,reset : IN STD_LOGIC SIGNAL sdatain : IN STD_LOGIC SIGNAL oready, sdataout : INOUT STD_LOGIC SIGNAL iready : INOUT STD_LOGIC SIGNAL charin : INOUT STD_L
shukongdianyabiao
- 使用51单片机以及键盘液晶作为人机互动，输入你想输入的电压值，端口就输出相应的二进制数-51 MCU and LCD using the keyboard as a human-computer interaction, input you want to input voltage value, the port on the output of the corresponding binary number
spmem.tar
- Sinlge port RAM VHDL/Verilog design
LCD12232disp
- LCD12232显示实验 编译环境是KEIL C51 mcu为AT89s51-LCD12232 show experimental build environment is KEIL C51 mcu for AT89s51
s6d0144_16
- 06D0144 LCM测试程序 51单片机-06D0144 LCM test program 51 MCU
dpmem2clk.tar
- Dual port memory VHDL/Verilog design
FIFO.tar
- FIFO design VHDL/Verilog design
mt48lc4m32b2.v
- SDRAM VHDL/Verilog simulation model
Stepldr
- 2443平台 使用三星64MDDR的NBOOT-2443 platform Samsung 64MDDR the NBOOT
pr
- FX WIN code to control PLC
mini2440_UM(090415)
- MINI2440 User Manual