资源列表
Jshuqi
- 基于VHDL原理图实现的计数器 时钟晶振为48MHZ -Schematic-based VHDL implementation of the counter clock oscillator is 48MHZ
1122
- 已经成功的FPGA 控制的SDRAM控制器代码.只要修改你需要的宽度-FPGA has been successfully controlled by SDRAM controller code. As long as you need to modify the width of
0011
- Altera_Sdram_IP_源码 可以参考的-Altera_Sdram_IP_ source for reference
Qdaqi
- 基于VHDL语言 实现八路抢答器 有源时钟48mhz 功能为任意按键按下屏蔽其它按键输入-VHDL language based on the active clock 48mhz eight Responder function to any button is pressed the other key input screen
3344
- BulkIn是FPGA向CY7C68013发送数据 BulkOut是FPGA从CY7C68013接收数据-BulkIn is the FPGA to send data to the CY7C68013 CY7C68013 BulkOut is receiving data from the FPGA
5566
- Alter官方FFT程序(使用Verilog编写)-Alter official FFT program (written using Verilog)
xuanze4x1
- 基于VHDL语言 4选1 多路选择器 时钟48Mhz 功能4个输入只能有一个输出-Based on VHDL, 4 to 1 MUX clock 48Mhz features 4 inputs can be only one output
7788
- 用verilog编写的1024点的fft快速傅立叶变换-Written in 1024 by verilog point fast Fourier transform fft
99000
- VerilogHDL课件 学习的好资料 可以参考-VerilogHDL Courseware good information can refer to
motion_detectionv1.0_1023
- 网络摄像头和硬盘录像机专用芯片gm8180代码-Web camera and DVR-specific code chip gm8180
EM78P468-NTC-lcd
- EM78P468 NTC lcd测温全套(C语言源代码)-EM78P468 NTC lcd full set temperature (C language source code)
uCOSIIV2.86
- uCOS-II原码,版本为V2.86.开源代码，供大家学习交流.-uCOS-II of the original code, version V2.86. open source code for all to study and exchange.