资源列表
m
- m序列产生器，verilog语言实现,在FPGA上试验过-m code maker
BitSynchronization
- 位同步信号提取，用verilog实现，经FPGA实验-Bit synchronization signal extraction, with verilog implementation
CPU-exp
- 基于VHDL编写的CPU程序，用微程序的方式实现。内含说明本程序的说明文档。-CPU program written in VHDL, with the micro-program ways.Containing the document of the program.
VerilogHDL-tutorial
- VerilogHDL硬件描述语言教程，较详细的介绍了verilog的基本用法-VerilogHDL hardware descr iption language tutorial, more detailed introduction to the basic usage of verilog
fpga-chengxu
- 对扩频通信系统的仿真程序，应用于fpga开发环境下-a simulation of Spread spectrum communication, using for fpga environment
Code
- 调试例程的主程序 用于开发版调通的程序 -Debug the main program for the development version of the routine procedures for transfer through
videocap
- 基于FPGA的视频采集源程序，完整代码，以供参考-FPGA-based video capture source, the complete code for reference
61-12864
- 通过凌阳spce061a开发板来控制lcd12864的汉字与图形的显示。-Sunplus spce061a through the development board to control the lcd12864 Chinese characters and graphics display.
3
- 4位数码管时钟 有秒、分、时 无掉电保存功能 -4-bit digital clock with seconds, minutes, saving time without power-down
yicishuru
- 4*4矩阵键盘扫描 从键盘输入0-F,在LCD上显示出来-4* 4 matrix keyboard scanning from the keyboard 0-F, displayed on the LCD
PPBEAR
- LCD1602 移动显示 LCD第一行显示： ilove 8051 mcu LCD第二行显示：13714407535 -LCD1602 LCD Mobile Display first line: ilove 8051 mcu LCD second line: 13714407535
code-and-result-for-66myfir
- 该附件为一基于VHDL语言的66阶FIR滤波器设计的整个过程和实验测试结果，对于相关开发人员和初学人员有很好的参考价值。-The Annex is a language based on VHDL-order FIR filter design 66 the whole process and experimental results, for the relevant developers and beginners who have a good reference value.