资源列表
fifo
- 采用verilog HDL语言实现FIFO的功能，内涵测试程序，有较强的使用性能。-Using verilog HDL language to achieve FIFO functionality, meaning the test program, there is a strong performance.
FPGA
- 该书详细的介绍了卷写FPGA开发软件的格式要求，实用性较强。-The book describes in detail the volume to write the format requirements of FPGA development software, practical, strong.
adder_latch
- 用verilog编写了一段地址锁存器的代码，希望能帮助大家！-Prepared using a verilog code address latch, hoping to help you!
code_element
- 总线控制器中接收部分的码元调制程序，希望能给大家带来帮助！-Bus controller to receive part of the symbol modulation process, I hope to give us some help!
e_32_16
- 8位串行数据转32位数据在转换为两个16位数据的verilog HDL代码。-8-bit serial data transfer 32-bit data into two 16-bit data verilog HDL code.
ads1675_if
- verilog时序图编写和测试代码，代码完整已经经过测试可以运行。-verilog timing diagram writing and testing code, the code has been tested to the full run.
tms320f28335_eqep_code
- DSP320f28335实现qep和pwm速度和位置计算的例程-the example code of tms320f28335 to calculate the speed and location
the-PID-for-dsp-6713
- pid在dsp6713中详细使用的应用源代码程序。-the pid code used in the DSP6713
genext2fs-1.4.1.tar
- A tool to make ramdisk
bf53x_audio_mp3decode
- 基于ADI DSP blackfin BF533开发板的MP3 音频解码程序-based on ADI DSP blackfin BF533， MP3 decoder
InvertedPd4_final
- DSP program for control inverted pendulm.