资源列表
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- pcb图 硬件设计图关于温度采集的，精读为1摄氏度-pcb diagram of the hardware design on the temperature acquisition, Intensive 1 degree Celsius
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- pcb图 硬件设计图关于温度采集的，精读为1摄氏度-pcb diagram of the hardware design on the temperature acquisition, Intensive 1 degree Celsius
158
- 温度采集 DS18B20 精度为1摄氏度然后采集温度范围是-55-1-The temperature acquisition DS18B20 an accuracy of The 1 degree Celsius and then acquisition the temperature the scope of yes-55-100
renjijiemian
- 实现理财,界面美观 采用GUI设计,实现登陆等可以使用的功能-account for a or some business ,and for some student in college to use
xiaoche
- 单片机的重要应用 学习单片机必要实践内容-Important application of SCM to learn the the SCM necessary practice content
pinlvji
- 使用verilog语言设计一个3位十进制数字式频率计，其测量范围为1MHz，量程为10kMz,100kMz和1MMz三档（最大读数分别为：9.99kMz，99.9kMz和999kMz）-Use verilog language, design a three decimal digital frequency meter
QuartusII
- QuartusII 相当全的文件，不能错过哦。-QuartusII users must save it!
4BITMULT
- 基于FPGA的四位乘法器，在QuartusII上编译通过可实现，采用VHDL语言编写。-Based on FPGA four on time-multiplier, in QuartusII compiled can be realized through, the VHDL language.
CODER
- 基于FPGA的8线-3线优先编码器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA eight line-3 line is preferred encoder design, QuartusII compile, USES the VHDL language.
DECODER7
- 基于FPGA的BCD/七段译码器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA BCD/these seven decoder design, QuartusII compile, USES the VHDL language.
adder
- 基于FPGA的加法器的设计，QuartusII编译通过，采用VHDL语言编写。-The adder on FPGA design, QuartusII compile, USES the VHDL language.
COUNT10
- 基于FPGA的一个带有异步复位和同步时钟使能的十进制加法计数器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA with a reduction of asynchronous and synchronous clock can make the decimal additions counter design, QuartusII compile, USES the VHDL language.