资源列表
how-to-config_pack_download-firmware-v1.0.doc
- Allwinner A10 Firmware configuration and packaging guide.
VHDL
- 电路主要由七个模块组成：时钟产生模块用于产生1KHz的扫描时钟和1Hz的时钟；二分频模块用于对1Hz的时钟信号二分频；测量/校验选择模块用于功能选择；计数模块用于对输入的cp信号计数；送存选择、报警电路根据选择的量程送存信号并显示单位，在超出所选量程时报警；锁存器锁存要显示的结果；扫描显示模块在1KHz的扫描时钟下，依次扫描三个数码管，并显示结果。-The circuit consists of seven main modules: clock generation module is use
si_xi_fen
- Quartus环境下，用verilog ＨＤＬ写的光电码盘的四细分程序，用于获得转向和转速-Quartus environment, use verilog HDL write light code disc four segmentation procedure, are used to obtain steering and speed
ad976
- FPGA实现AD976的自动采样的Verilog HDL程序，所采用的是AD976的模式一，已调试成功-AD976 FPGA to realize the automatic sampling of the verilog HDL program, the is AD976 model a, already debugging success
ad976_CS
- FPGA实现AD976的自动采样的Verilog HDL程序，所采用的是AD976的模式二，即采用CS信号，已调试成功-AD976 FPGA to realize the automatic sampling of the Verilog HDL program, the AD976 is the mode 2, i.e., to use the CS signal, already debugging success
1602
- VHDL实现的1602液晶显示程序，已调试成功-VHDL realization of 1602 liquid crystal display program, already debugging success
RS232
- VHDL实现的RS232通信程序，发送和接收都已实现-VHDL realization of RS232 communication procedures, send and receive are realized
arp1
- 实现arp协议的设置，初学者可以试试，但是有的地方需要修改，还的加强-Achieve set of arp agreement, beginners can try, but some places need to be modified, the strengthening of the harm
Control
- 单片机操作，实现两个串口，两个时间中断，在这个过程中中进行工业控制过程-Microcontroller operation, two serial ports, two time interrupts this process in industrial control process
DS18B20V1.3
- MPC82G516的DS18B20操作！-MPC82G516 the the DS18B20 operation!
UART2.0
- MPC82G516的UART串口通信！收发正常！并带有printf输出到串口显示-MPC82G516 UART serial communication! Send and receive normal! With printf output to the serial port and display! ! !
DS1302V1.3
- MPC82G516的DS1302时钟芯片的读写，并附带串口读写时间！-MPC82G516 the DS1302 clock chip to read and write, and comes with a serial read and write time!