资源列表
Function_clock_generate
- 基于FPGA实现的实时闹钟，在DE2—115开发板上通过验证，实现报时，定时，时间调整等功能-Based on verified DE2-115 development board FPGA to achieve real-time alarm, timekeeping, timing, time adjustment
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
24c64_c
- 主要是针对eeprom的芯片24c64编写而成的源代码，具有一点的参考意义。-The main source code written for the eeprom the chip 24c64, has little significance.
rc_flt
- 基于FPGA实现的64阶升余弦FIR并行滤波器，采用iso18000.6c标准实现，具有很好的低通滤波效果，已通过后仿上板验证，采用verilog语言实现。-64 order raised cosine FIR FPGA-based parallel filters, implemented using iso18000.6c standard with a low-pass filtering effect imitation on the board has passed validatio
uart_regs
- 通过动手实践，熟悉使用Quartus II设计FPGA的方法-By hands-on practice, familiar with the method of using Quartus II design FPGA
Project
- 通过动手实践，熟悉Altera基本宏功能的产生和实现方法-Incurred and realized by hands familiar with Altera Basic macro functions
video_systems.tar
- H264 decoder on Stratix VI-H264 decoder
develop_frame_find
- 基于FPGA中OFDM中的帧检测，由于采用简化算法，采用较少的复数乘法器，易于硬件实现，且节省资源，采用verilog实现.-Frame detection based on FPGA for OFDM, a simplified algorithm, using less complex multiplier, easily implemented in hardware, and save resources, the SNR performance is slightly lower th
802.15.4
- 无线通信协议802.14 协议C语言实现-The wireless communication protocol of the 802.14 protocol C-language ......................................................
develop_Phase_Tracking
- 基于FPGA实现，OFDM基带通信中的剩余相位检测，具有很好的性能，采用verilog语言。-FPGA-based the remaining OFDM baseband communication phase detection, has a very good performance, verilog language.
89c52_MAX485
- 单片机与max485通信的源代码单片机与max485通信的源代码-this is a max485 solftware
findID
- 单片机查找DS18B20的ID号的程序，可以实现一条总线上挂接多个DS18B20.-SCM Find DS18B20 the ID number of the program, can mount multiple DS18B20 a bus.