资源列表
addsub32bit
- 32bit floating point addition
shumaguandongtai
- VHDL的动态扫描显示六个数码管，包含分频代码产生25kHz的扫描信号作为时钟。-VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.
clock
- verilog编写的8位数码管时钟，可现实秒，分，时-8 digital tube clock written in verilog reality of seconds, minutes, hours
traffic
- 东南大学信息学院大三编程课，VHDL相关交通灯大作业相关代码。欢迎指教改正-Southeast University, School of Information junior programming class job code for the VHDL traffic lights. Welcome advice corrections
DE2_pin
- DE2控制面板 液晶显示验证代码 用verilog 语言描写的-this is a control panel about LCD s display expierents
arm7_6500_keil_print_emi
- ARM7内核，EMI模块测试程序，用于FPGA测试，内含print功能-ARM7 core, the EMI module testing procedures for FPGA test, containing the print function
arm7_6500_keil_print_wdg
- ARM7环境下watchdog模块测试程序，自带print功能-ARM7 environment watchdog module test procedures, its own print function
kb_monitor
- 用rs-232 cable 將ps/2鍵盤資訊傳送到pc-look up kb scan code in pc through rs-232 cable
clock-divider
- clock generator vhdl code
Rs232-reciever
- RS232 reciver vhdl code for RS232 EIA232-RS232 reciver vhdl code for RS232 EIA232
ads1282_code
- 用VHDL写的控制TI公司32位高精度ADC的程序，可以可靠运行，已经应用于实际项目-Control TI' s 32-bit precision ADC program written using VHDL, reliable operation, has been applied to the actual project
counter
- 基于FPGA的计数器程序涉及，可以自由移植使用-Transplantation using FPGA-based counter program involves freedom