资源列表
clock3
- VHDL语言编写的带整点报时的8段数码管数字时钟-Digital clock VHDL language with hourly chime
light
- VHDL的简单流水灯程序，实现八段数码管从中间到两边再从两边到中间依次点亮-VHDL simple light water program, eight digital tube from the middle to both sides from both sides to the middle followed by light
595
- 这个是基于单片机开发板上的C语言练习程序-This is based on the microcontroller development board
SERIAL_asm
- UART Assembly langauage Progam for P89V51 using IAR Compiler
vga_3bits
- 3位宽的vga接口的verilog代码，调试通过，在FPGA上可以综合。-3-bit wide vga interface verilog code, debugging through, can be integrated on the FPGA.
8x8lcd
- proteus 单片机c51 8x8点阵仿真。对学单片机的同学很有用。 -proteus microcontroller c51 8x8 dot matrix simulation. Classmates useful school microcontroller.
fpga
- fpga implementation of basic program
batch-26
- VHDL CODING FOR BASIC DIGITAL CIRCUITS
mimasuo
- 用AT89C51单片机为核心控制元件，设计一个电子密码锁。用24C04保存密码，在输入正确密码时，开锁亮灯，液晶屏显示开锁成功，开锁成功后用户可按下重设密码键设置新密码，在输入新密码后按下存入键将新密码写入24C04，下次开锁时用新密码才能打开。-AT89C51 microcontroller as the core control element, the design of an electronic combination lock. 24C04 save password, enter
VHDL-divider-design
- VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-cr
STR750-SK_LCD
- STR750-SK_LCD.ST ARM 程序，已经调试通过，对开发人员有很大的参考帮助-The the STR750-SK_LCD.ST ARM program debugging has been passed, a lot of reference to help developers
STR750-SK_LedBlink
- STR750-SK_LedBlink.ST ARM 程序，已经调试通过，对开发人员有很大的参考帮助-The the STR750-SK_LedBlink.ST ARM program debugging has been passed, a lot of reference to help developers