资源列表
1802-bell-liangzhu
- 基于FPGA的音乐播放器，采用VHDL语言-FPGA-based music player, using VHDL language
DS18B20stm32readtemp
- stm32读取单总线上6个DS18B20的温度数据，显示在液晶屏上（6个DS18B20的ID已知的情况）-stm32 read on a single bus 6 DS18B20 temperature data is displayed on the LCD screen (6 DS18B20 known case of ID)
temp
- 基于FPGA的一个温度传感系统 用verilog语言编写 基于basys2开发板-FPGA verilog basys2
AD
- 基于FPGA的AD采集系统 用verilog编写 基于basys2开发板-FPGA AD verilog basys2
DA
- DA转换 基于FPGA 用verilog编写 基于basys2开发板-DA FPGA VERILOG BASYS2
CpuTimer0
- dsp定时器0测试程序，定时器计时到1000ms时，产生中断，进入中断服务子函数，改变电平，实现led灯闪烁效果-dsp test program Timer 0, timer counting to 1000ms, generate an interrupt, the interrupt service subroutine, changing the level, realize led lights flicker effect
i2c_adv7180
- ADV7180的i2c驱动程序，VHDL语言开发，有详细注释，适合初学者学习和参考。-ADV7180 i2c driver, VHDL language development, have detailed comments, suitable for beginners learning and reference.
AD-DA
- dsp片内ad初始化，模数转换功能，包括DAC信号产生和ad采样信号程序-within dsp chip ad initialization, analog to digital conversion functions, including signal generation and ad DAC sampling signal program
PWM
- 利用dsp的事件管理器模块EVA产生pwm信号，通过改变周期存储器值和系统时钟可以改变pwm周期，占空比等参数-Use dsp event management module EVA produces pwm signal, by changing the value of the memory and the system clock cycle can change pwm period, duty cycle and other parameters
MemoryBIST
- memory的BIST代码，verilog-The memory BIST codes, verilog
xiao-che-de-che-ti
- 关于设计多功能小车的车体部分的源码，有关于电机等的。-About the design of multi-function car body part of the source, about motor etc.
asdf
- dsp2812的串口通信例程，232的查询方式的，调试成功的-dsp2812 serial communication routines, query 232, commissioning successful