资源列表
clk_generator
- 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
clock
- 51单片机，6位数码管时钟，按键可调节时间，包括proteus仿真图-51 single-chip, six digital clocks, buttons to adjust the time, including proteus simulation map
absolute2relative_coding
- ISE编程仿真DPSK中相对码和绝对码的转换-DPSK code conversion relative and absolute code
squa
- Verilog语言ISE下实现方波产生和占空比调节-ISE Verilog language implementations under wave generator
counter6display
- ISE环境下Verilog变成实现六位计数器并用7段显像管显示-ISE Verilog environment becomes realized under six counter with 7-segment display CRT
coubter_key
- ISE环境下Verilog编程实现机械按键去抖-ISE Verilog programming environment under mechanical debounces
12864draw_point
- 12864画点程序，从51移植，支持nios2-drawpoint 12864
cnt63dis
- ISE环境下Verilog编程实现63进制计数器并用7段译码显像管显示-ISE Verilog programming environment under 63 binary counter with 7 segment decoder CRT display
addafilter
- 基于NIOSii的数字滤波器，包括AD和DA的读取输出部分，包括C语言源码和verilog源工程-digital filter based on Nios2
digitron
- 数码管显示，里面包含了译码器等多用电路的源码和顶层电路图，并最后进行了组合。-Digital display, which contains the source code and many other top level schematics decoder circuit and finally a combination.
digitron
- 数码管显示工程，里面包含了译码器等多用电路的VHDL源码和顶层电路图，并最后进行了组合。-Digital display, which contains the source code and many other top level schematics decoder circuit and finally a combination.
STC15F104W_STCDOWN
- 用STC15F104W实现对目标STC芯片免冷启动下载控制...原理: 检测STC-ISP下载程序的下载指令, 当连续检测到指令7F, 则通过控制三极管8550对电源断开再上电,实现免冷启动-use stc15F104W control power