资源列表
verilog
- 用verilog设计的寄存器，储存器，锁存器，译码器以及在其中用到的八位串联并联间的相互转换。-Verilog design registers, memory, lock latch decoder and the use of eight series parallel conversion
Timing-
- 利用verilog设计的停车场中的计数器计时器和计费器，完成智能管理效果-Use the counter timer and meter parking lot in the Verilog design, intelligent management
HR202
- 基于HR202的测湿程序,包含详细的程序解释，比其他类似程序更精确。-Based on the HR202 moisture program, contains detailed procedures explain, more accurate than other similar programs.
4bit_SD
- 4-bit模式下SD卡的读写，只是一个函数，不是整整个工程-4-bit SD mode，write a single block，just a function，not entire project
RTClib
- library ds1307 for arduino
traffic
- 学习VHDL语言入门程序——交通灯。对理解时序关系和VHDL基本语法很有帮助。-Learning VHDL language entry procedures- traffic lights. Understanding of the relationship between the timing and VHDL basic grammar.
clock
- 利用VHDL语言实现了时、分、秒的计时，并在七段数码管显示出来。-Using VHDL language realize the hours, minutes and seconds of time, and in the seven-segment LED display.
dac_900
- DAC900芯片驱动的Verilog语言描述，亲测可用。另外的是FIR滤波代码和DDS波形发生器的代码。既可单独使用，也可以整合在一起。-DAC900 chips driven Verilog language descr iption, pro-test available. Another is the FIR filter code and DDS waveform generator code. Either used alone or can be integrated.
ads822
- 自己用Verilog语言写的ADS822芯片的驱动，亲测可用。其他并行ADC芯片也可以用。-Verilog language used to write their own drivers ADS822 chips, pro-test available. Other parallel ADC chips can also be used.
dual_ram
- 在ISE中测试双端口RAM的源码，结合DDS可以通过Isim仿真直接测试RAM IP核的使用是否正常。-Dual-port RAM test source code in ISE, the binding DDS RAM IP core can be directly tested whether the use of the normal simulation.
EPS_1200C
- 单片机逆变器源程序，保护功能很好，已大批量生产过。- unsigned int OUT_T,charge_cut,charg_c,Output_Load,Output_LoadC,con_Curr,AC_frequency,ch_Bat,out_v,Bat_c,Shutdown_T,ADC_Value
UPS_1K2D
- UPS-1200D 源程序,智能在线后备式，全自动型经批量生产 -charge_cut,dis_V_FLAG,dis_ACdata,dis_V,Output_Load,Output_LoadC