资源列表
PWM-IN-and-OUT
- 飞思卡尔全国大学生智能车大赛摄像头组PWM的输入输出程序-National Students Contest Freescale Smart Car camera group PWM input and output procedures
80c51-hongwaiyaokong
- 实现80c51的红外遥控控制功能，可以通过红外遥控器控制继电器的开断，步进电机的开关，并且可以遥控调节电机转速，使用时，通过数码管可显示红外遥控信号的客户码，指令码，可以与电视机遥控器配对来控制-80c51 achieve infrared remote control functions can be controlled by infrared remote control relay breaking, stepper motor switch, and remote control ca
20160620---DS1302test
- 高质量的完整DS1302日历（阳历）keil程序，显示部分采用LCD1602，输入控制采用串口，每个部分均采用模块化可移植性强的代码书写方式。经测试在5V系统下工作正常。芯片采用STC12C5A60S2。-High quality of the complete DS1302 calendar (Yang Li) keil program, the display part of the use of LCD1602, the input control using the serial por
lms_adaptive_filter.vhd
- lms adaptive filter using desired and input stream to get the output with 4 tabs filter.
plj1
- 通过C51单片机测试输入波形的频率，并在LCD1602上显示对应频率数值-The frequency of the input waveform is tested by C51 single-chip microcomputer, and the corresponding frequency value is displayed on the LCD1602.
LCD12864详细代码
- LCD12864详细代码，喜欢的朋友淡定下载；无毒
udp_offload
- altera udp 开发参考，ep3c120f720c7，内涵qsys系统，nios 代码-altera udp Development Reference, ep3c120f720c7, connotation qsys system, nios Code
ddr2
- ddr2 仿真模型，适应于modelsim 仿真，内涵仿真核源码-ddr2 simulation model adapted to the modelsim simulation, simulation connotation nuclear source
timing_constraint
- 三速以太网时序约束参考设计，内涵quartus ii 工程，sdc文件-Triple-Speed Ethernet reference design timing constraints, content quartus ii project, sdc file
ASI
- 异步串行接口ASI,QUARTUS cv demo参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI, QUARTUS cv demo reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
ASI_simulation
- 异步串行接口ASI仿真设计,quartus modelsim 仿真参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI simulation design, quartus modelsim simulation reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
IPC_example_on_6678
- 多核6678dsp的核间中断的裸板程序，通过对相应的核中断寄存器置位来触发中断核间相互触发中断-Multicore 6678dsp between nuclear program interruption bare board, through the corresponding core is set to trigger an interrupt register interrupt the nuclear trigger interrupt each other