资源列表
xst3_video
- 珍藏多年视频GAME之VHD学习资料5-VIDEO GAME VHDL
ug176
- ug-series servovalve
lv-maxsonar-ez
- With 2.5V - 5.5V power the LV-MaxSonar® - EZ1™ provides very short to long-range detection and ranging, in an incredibly small package. The LV-MaxSonar® -EZ1™ detects objects 0-inches to 254-inches (6.45-meters) and provi
an-102104-keybrd
- VHDL 键盘一些有用的学习资料, 真的很有价值-VHDL KEY BOARD
ug133a
- russian ug-series servovalve
nRF24L01Pluss_Preliminary_Product_Specification_v
- 24lo1 radio-chip specification
dpll
- 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis
mac_layer_switch_latest.tar
- source code for Ethernet logic
e1framerdeframer_latest.tar
- E1 framer logic implementaion
adaptive_lms_equalizer_latest.tar
- adaptive lms equaliser
all-pole_filters_latest.tar
- all pole filter for dsp
biquad_latest.tar
- IIR filter with two poles and two zeros